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參數資料
| 型號： | S71WS-N |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) |
| 中文描述： | 堆疊式多芯片產品（MCP） |
| 文件頁數： | 7/13頁 |
| 文件大?。?/td> | 186K |
| 代理商： | S71WS-N |
July 19, 2006 S71WS-N_00_A6
S71WS-N
5
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
4.
MCP Block Diagram
Notes:
1. R-CRE is only present in CellularRAM-compatible pSRAM.
2. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash.
3. Only needed for S71WS512N.
4. For the 128M pSRAM devices, there are 23 shared addresses.
5.
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S71WS-N.
5.1
Special Handling Instructions for FBGA Packages
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
VID
VCC
DQ15 to DQ0
RDY
pSRAM
Flash 1
(
Note 4
)
DQ15 to DQ0
Flash-only Address
Shared Address
F1-CE#
(
Note 2
)
ACC
R-UB#
R-LB#
R-CE2
R-CRE
(
Note 1
)
R-VCC
V
CC
V
CCQ
F-VCC
22
CLK
WP#
CLK
OE#
WE#
F-RST#
AVD#
CE#
OE#
WE#
RESET#
AVD#
ACC
WP#
RDY
V
SS
VSSQ
16
I/O15 to I/O0
16
R-CE1#
CE#
WE#
OE#
UB#
LB#
22
F2-CE#
(
Note 2
)
CLK
AVD#
CRE#
Flash 2
WAIT#
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