參數資料
型號: S71PL129JB0BFW9P2
廠商: Spansion Inc.
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory
中文描述: 堆疊式多芯片產品(MCP)的快閃記憶體
文件頁數: 147/149頁
文件大小: 2693K
代理商: S71PL129JB0BFW9P2
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
147
A d v a n c e i n f o r m a t i o n
Note:
Both t
CHOX
and t
CHWX
define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
t
RC
(min) period for Standby mode from CE1# Low to High transition.
Figure 72. Standby Entry Timing after Read or Write
Notes:
1.
The all address inputs must be High from Cycle #1 to #5.
2.
The address key must confirm the format specified in page 132. If not, the operation and data are not guaranteed.
3.
After t
CP
following Cycle #6, the Power Down Program is completed and returned to the normal operation.
Figure 73. Power Down Program Timing (for 32M/64M Only)
t
CHOX
CE1#
OE#
WE#
Active (Read)
Standby
Active (Write)
Standby
t
CHWX
ADDRESS
CE1#
DQ*
3
WE#
t
RC
OE#
LB#, UB#
RDa
MSB*
1
MSB*
1
MSB*
1
MSB*
1
MSB*
1
Key*
2
t
WC
t
WC
t
WC
t
WC
t
RC
t
CP
t
CP
t
CP
t
CP
t
CP
t
CP
*
3
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
RDa
RDa
X
X
RDb
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