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參數(shù)資料
| 型號： | S71PL129JB0BAI9Z2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA64 |
| 封裝： | 8 X 11.60 MM, 1.20 MM HEIGHT, FBGA-64 |
| 文件頁數(shù)： | 5/149頁 |
| 文件大?。?/td> | 2693K |
| 代理商： | S71PL129JB0BAI9Z2 |
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December 23, 2004 S71PL129Jxx_00_A5
5
A d v a n c e I n f o r m a t i o n
DC and Operating Characteristics . . . . . . . . . . . 121
Common ...............................................................................................................121
16M pSRAM .........................................................................................................122
32M pSRAM ........................................................................................................122
64M pSRAM ........................................................................................................123
128M pSRAM .......................................................................................................123
AC Operating Conditions . . . . . . . . . . . . . . . . . 124
Test Conditions (Test Load and Test Input/Output Reference) .......124
Figure 45. Output Load ..................................................... 124
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126
Read Timings ......................................................................................................126
Figure 46. Timing Waveform of Read Cycle(1)...................... 126
Figure 47. Timing Waveform of Read Cycle(2)...................... 126
Figure 48. Timing Waveform of Page Cycle (Page Mode Only) 127
Write Timings ....................................................................................................127
Figure 49. Write Cycle #1 (WE# Controlled) ........................ 127
Figure 50. Write Cycle #2 (CS1# Controlled) ....................... 128
Figure 51. Timing Waveform of Write Cycle(3)
(CS2 Controlled) .............................................................. 128
Figure 52. Timing Waveform of Write Cycle(4) (UB#, LB#
Controlled) ...................................................................... 129
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Functional Description . . . . . . . . . . . . . . . . . . . . . 131
Power Down (for 32M, 64M Only) . . . . . . . . . . . . 131
Power Down .......................................................................................................131
Power Down Program Sequence .................................................................132
Address Key .......................................................................................................132
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 133
Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 133
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 134
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 135
Read Operation ..................................................................................................135
Write Operation ...............................................................................................136
Power Down Parameters ...............................................................................137
Other Timing Parameters ...............................................................................137
AC Test Conditions .........................................................................................138
AC Measurement Output Load Circuits ...................................................138
Figure 53. AC Output Load Circuit – 16 Mb.......................... 138
Figure 54. AC Output Load Circuit – 32 Mb and 64 Mb.......... 138
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139
Read Timings .......................................................................................................139
Figure 55. Read Timing #1 (Basic Timing) .......................... 139
Figure 56. Read Timing #2 (OE# Address Access................. 139
Figure 57. Read Timing #3 (LB#/UB# Byte Access) ............. 140
Figure 58. Read Timing #4 (Page Address Access after CE1#
Control Access for 32M and 64M Only) ............................... 140
Figure 59. Read Timing #5 (Random and Page Address Access for
32M and 64M Only) ......................................................... 141
Write Timings ......................................................................................................141
Figure 60. Write Timing #1 (Basic Timing) .......................... 141
Figure 61. Write Timing #2 (WE# Control).......................... 142
Figure 62. Write Timing #3-1
(WE#/LB#/UB# Byte Write Control) .................................. 142
Figure 63. Write Timing #3-3
(WE#/LB#/UB# Byte Write Control) .................................. 143
Figure 64. Write Timing #3-4
(WE#/LB#/UB# Byte Write Control) .................................. 143
Read/Write Timings ..........................................................................................144
Figure 65. Read/Write Timing #1-1 (CE1# Control) ............. 144
Figure 66. Read / Write Timing #1-2
(CE1#/WE#/OE# Control) ................................................ 144
Figure 67. Read / Write Timing #2 (OE#, WE# Control) ....... 145
Figure 68. Read / Write Timing #3
(OE#, WE#, LB#, UB# Control) ........................................ 145
Figure 69. Power-up Timing #1 ......................................... 146
Figure 70. Power-up Timing #2 ......................................... 146
Figure 71. Power Down Entry and Exit Timing ..................... 146
Figure 72. Standby Entry Timing after Read or Write............ 147
Figure 73. Power Down Program Timing (for 32M/64M Only) . 147
Revision Summary
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PDF描述 |
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| S71PL129JB0BAI9Z3 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BFI9B0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BFI9B2 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JC0 | Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JC0BAI9Z2 | Stacked Multi-Chip Product (MCP) Flash Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S71PL129JB0BAI9Z3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BAW9B0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BAW9B2 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BAW9B3 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
| S71PL129JB0BAW9P0 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory |
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