參數(shù)資料
型號: S71PL064JB0BFW0U0
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA56
封裝: 9 X 7 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56
文件頁數(shù): 13/22頁
文件大?。?/td> 712K
代理商: S71PL064JB0BFW0U0
20
S71PL-J Based MCPs
S71PL-J_00_B5 July 17, 2007
Da ta
Sh e e t
8.
Revision History
Section
Description
Revision A (May 3, 2004)
Initial release
Revision A1 (May 6, 2004)
Features
Corrected the high performance access times.
Connection Diagrams
Added reference points on all diagrams.
Ordering Information
Corrected package types.
Corrected the description of product family to Page Mode Flash memory.
Revision A2 (May 11, 2004)
General Description
Corrected the tables to reflect accurate device configurations.
Revision A3 (June 16, 2004)
Ordering Information
Corrected the Valid Combinations tables to reflect accurate device configurations.
Revision A4 (July 16, 2004)
Global
Global Change of FASL to Spansion.
Global change to remove space between M and Mb callouts.
32 Mb Flash Memory
Replaced “S71PL032J08-07” with “S71PL032J08-0B”.
Replaced “S71PL032JA0” with “S71PL032JA0-07”.
Replaced “S71PL032JA0-08” with “S71PL032JA0-0F”.
Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70; pSRAM3; TLC056.
64 Mb Flash Memory
Replaced “S71PL064J08-0K” with “S71PL064J08-0B”.
Replaced “S71PL064J08-0P” with “S71PL064J08-0U”.
Deleted “S71PL064J80-05” row.
Replaced “S71PL064JA0-07” with “S71PL064JA0-0K”.
Replaced “S71PL064JA0-0Z” with
Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram 1; TLC056.
128 Mb Flash Memory
Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70; pSRAM; TLA064.
Replaced “S71PL127JB0-97” with “S71PL127JB0-9Z”.
Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70; pSRAM1; TLA064.
Replaced “S71PL127JC0-9P” with “S71PL127JC0-9Z”.
In the S71Pl254JB0-TB row changed pSRAM type from “pSRAM3” to “pSRAM2”.
256 Mb Flash Memory
Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70; pSRAM3; FTA084.
Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70; pSRAM2; FTA084.
Connection Diagrams
Updated pins D8, D9, and L5.
Added notes 2 and 3 to drawing.
Updated pins D8 and D9.
Added Note 2 to drawing.
S71PL032J Valid Combinations
Changed S71PL032J08 (p)SRAM Type Access Time (ns) from “SRAM1” to “SRAM2” (4 changes
made in table).
Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from “SRAM3 / 70” to pSRAM3 /70”.
Deleted all cells with the following collaborated text: “BAW,BFW, BAI. BFI”. Merged previous place
holder with cell above.
S71PL064J Valid Combinations
In (p)SRAM Type/Access Time (ns) changed all instances of “stet” to “pSRAM1/70”.
In Package Modifier/Model Number changed all instances of “stet” to “07”.
Added row to BAW Package and Temperature sections with the following content: S71PL064JB0;
07; 65 (previously inclusive); pSRAM1/70.
S71PL127J Valid Combinations
Changed the S71PL127JA0 Package Modifier/Model Number from “9Z” to “9P” (4 instances).
Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70.
S71PL254J Valid Combinations
Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70.
Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70.
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