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參數(shù)資料
| 型號： | S6C0649 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256 CHANNEL TFT-LCD GATE DRIVER |
| 中文描述： | 256個頻道的TFT - LCD柵極驅(qū)動器 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 118K |
| 代理商： | S6C0649 |
256 CH. TFT-LCD GATE DRIVER
S6C0649
7
PIN DESCRIPTIONS
Symbol
Pin Name
I / O
Description
DI/O
DO/I
Start pulse input/output
I / O
When these inputs operate as the input, the start pulse data is
read at the rising edge of shift clock, CPV.
When these inputs operate as the output, the start pulse output
is the next chip’s start pulse input. The output pulse is
generated
at the falling edge of the 256th shift clock, CPV.
When U/D = H, the shift register does right shifting operation.
(Input = DI/O and output = DO/I)
When U/D = L, the shift register does left shifting operation.
(Input = DO/I and output = DI/O)
When U/D = H, DI/O
→
G001
→……→
G256
→
DO/I
When U/D = L, DO/I
→
G256
→……→
G001
→
DI/O
The shift register operates in synchronization with the rising
edge of this input
These inputs control the state of the driver outputs.
When OE = H, the driver output is fixed to VSS2.
When OE = L, the driver output is VGG or VSS2 corresponding
to the data.
The output signals change in synchronization with the rising
edge of shift clock input, CPV.
The amplitude of the driver output is VGG - VSS2.
The input is internally connected to the logic ground, VSS1.
The input operates as the TFT panel gate OFF voltage.
Logic input range: VDD - VLO
6 to 35 V
The TFT gate ON voltage is VGG - VSS2.
2.7 to 5.5 V
The logic negative power supply, VSS1, is internally connected
to the driver negative power supply, VSS2.
U/D
Shift direction control input
I
CPV
Shift clock input
I
OE1
OE2
OE3
Output enable input
I
G001
to
G256
Driver output
O
VSS2
Driver negative power supply
I
VLO
Logic input low voltage
I
VGG
Driver positive power supply
I
VDD
Logic positive power supply
I
VSS1
Logic negative power supply
I
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