參數(shù)資料
型號(hào): S6B2104
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 80CH SEGMENT DRIVER FOR DOT MATRIX LCD
中文描述: 80CH段驅(qū)動(dòng)的點(diǎn)陣LCD
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 122K
代理商: S6B2104
S6B2104
80CH SEGMENT DRIVER FOR DOT MATRIX LCD
8
PIN DESCRIPTION
Table 1. Pin Description
Pin No
VDD (40)
VSS (42)
VEE (33)
I/O
Power Operating voltage
Negative supply
voltage
I
LCD driver output
voltage level
Name
Function
Interface
For logical circuit (+5V
±
10%, +3V
±
10%)
0V (GND)
For LCD drive circuit
Power
Supply
V1, V3, V4
(34-36)
Bias supply voltage terminals to drive the LCD.
Bias voltage divided by the resistance is usually used
as supply voltage source. (refer to note 1)
Display data output pin which corresponds to the
respective latch contents. One of V1, V3, V4 and VEE
is selected as a display driving voltage source
according to the combination of the latched data level
and M signal (refer to note 2)
Clock pulse input for the 4 bit parallel shift register.
The data is shifted to 80 bit shift register at the falling
edge of the clock pulse. The clock pulse, which was
input when the enable bit (EIB/EOB) is not active
condition, is invalid.
Alternate signal input pin for LCD driving.
Normal frame inversion signal is input
The signal for latching the shift register contents is
input to this terminal. CL1 pulse "H" level initializes
power-down function block.
Control input pin for display data output level (S1-
S80). V1 level is output from S1-S80 terminal during
"L" level input. LCD becomes non-selected by V1 level
output from every output of segment drivers and every
output of common drivers.
EOB and EIB can be used as either input terminal or
output terminal according to the condition of SHL. The
shifting direction of each data, D0-D3, the I/O
condition of EOB and EIB, and the condition of SHL
are described in the table below. (refer to note 3).
Power
S1-S80
(1-30,
51-100)
O
LCD driver output
LCD
CL2 (47)
I
Data shift clock
Controller
M (38)
I
Alternate signal for
LCD driver output
Data latch clock
Controller
CL1 (49)
I
Controller
DISPOFFB
(39)
I
Output level
control
(Display off)
Controller
SHL (41)
I
Data shift control
VDD/VSS
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