參數(shù)資料
型號: S5T8702X01-E0R0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: FEEX ALPHANUMERIC DECODER II
中文描述: FEEX字母數(shù)字解碼器二
文件頁數(shù): 8/62頁
文件大?。?/td> 444K
代理商: S5T8702X01-E0R0
S5T8702
FEEX
TM
ALPHANUMERIC DECODER II
8
FUNCTIONAL DESCRIPTION
SPI PACKETS
All data communicated between the S5T8702 and the host MCU is transmitted on the SPI in 32-bit packets. Each
packet consists of an 8-bit ID followed by 24 bits of information. The S5T8702 uses the SPI bus in full duplex
mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data.
The SPI interface consists of a
chip select for the S5T8702. The
SCK
is a clock supplied by the host MCU. The data from the host is transmitted
on the
MOSI
(Master-Out-Slave-In) line. The data from the S5T8702 is transmitted on the
MISO
(Master-In-Slave-
Out) line.
READY
pin and four SPI pins (
SS
, SCK, MOSI
, and
MISO
). The
SS
is used as a
Timing requirements for SPI communication are specified in
"
SPI Timing
"
on page 60.
PACKET COMMUNICATION INITIATED BY THE HOST
Refer to figure 6 on page 10. When the host sends a packet to the S5T8702, it performs the following steps:
1.
Select the S5T8702 by driving the
SS
pin low.
2.
Wait for the S5T8702 to drive the
READY
pin low.
3.
Send the 32-bit packet.
4.
De-select the S5T8702 by driving the
SS
pin high.
5.
Repeat steps 1 through 4 for each additional packet.
D31
D1
D0
D31
D1
D0
D31
D1
D0
D31
D1
D0
D31
D1
D0
D31
D1
D0
High-impedance State
MISO
MOSI
SCK
READY
SS
1
2
3
4
Figure 6: Typical Multiple Packet Communications Initiated by the Host
When the host sends a packet, it will also receive a valid packet from the S5T8702. If the S5T8702 is enabled
(see
"
Checksum Packet" on page 15 for a definition of enabled) and has no other packets waiting to be sent, the
S5T8702 will send a status packet.
The host must transition the
SS
see a negative transition on the
pin from high to low to begin each 32-bit packet. The S5T8702 must
SS
pin in order for the host to initiate each packet communication.
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