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參數(shù)資料
| 型號： | S5933 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI MatchMaker |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 174K |
| 代理商： | S5933 |
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
7
S5933
32-Bit PCI “MatchMaker”
S5933 P
IN
D
ESCRIPTIONS
AD[31:0]
t
/s
Address/Data.
Address and data are multiplexed on the same PCI bus pins. A PCI Bus
transaction consists of an address phase followed by one or more data phases. An address
phase occurs on the PCLK cycle in which FRAME# is asserted. A data phase occurs on
the PCLK cycles in which IRDY# and TRDY# are both asserted.
C/BE[3:0]#
t/s
Bus Command/Byte Enable
. Bus commands and byte enables are multiplexed on the same
pins. These pins define the current bus command during an address phase. During a data
phase, these pins are used as Byte Enables, with C/BE[0]# enabling byte 0 (LSB) and C/
BE[3]# enabling byte 3 (MSB).
C/BE# [3 2 1 0] Description
0 0 0 0 Interrupt Acknowledge
0 0 0 1 Special Cycle
0 0 1 0 I/O Read
0 0 1 1 I/O Write
0 1 0 0 Reserved
0 1 0 1 Reserved
0 1 1 0 Memory Read
0 1 1 1 Memory Write
1 0 0 0 Reserved
1 0 0 1 Reserved
1 0 1 0 Configuration Read
1 0 1 1 Configuration Write
1 1 0 0 Memory Read Multiple
1 1 0 1 Dual Address Cycle
1 1 1 0 Memory Read Line
1 1 1 1 Memory Write and Invalidate
PAR
t/s
Parity
. Parity is always driven as even from all AD[31:0] and C/BE[3:0]# signals. The par-
ity is valid during the clock following the address phase and is driven by the bus master.
During a data phase for write transactions, the bus master sources this signal on the clock
following IRDY# active; during a data phase for read transactions, this signal is driven by
the target and is valid on the clock following TRDY# active. The PAR signal has the same
timing as AD[31:0], delayed by one clock.
PCLK
in
Clock
. The rising edge of this signal is the reference upon which all other signals are based
except for RST# and INTA#. The maximum PCLK frequency for the S5933 is 33 MHz
and the minimum is DC (0 Hz).
RST#
in
Reset
is used to bring all other signals within the S5933 to a known, consistent state. All
PCI bus interface output signals are not driven (tri-stated), and open drain signals such as
SERR# are floated.
FRAME#
s/t/s
Frame
. This signal is driven by the current bus master to indicate the beginning and dura-
tion of a bus transaction. When FRAME# is first asserted, it indicates a bus transaction is
beginning with a valid addresses and bus command present on AD[31:0] and C/BE[3:0].
FRAME# remains asserted during a burst data transfer and is deasserted to signify the
final data phase.
IRDY#
s/t/s
Initiator Ready
. This signal is always driven by the bus master to indicate its ability to
complete the current data phase. During write transactions, it indicates AD[31:0] contains
valid data. Wait states occur until both TRDY# and IRDY# are asserted together.
相關(guān)PDF資料 |
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|---|---|
| S5935_07 | PCI Product |
| S5935QRC | PCI Product |
| S5935TFC | PCI Product |
| S5935TF | PCI 5V Bus Master/Target Device 32-bit |
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5933QC | 制造商:AMC 功能描述:IC |
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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