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參數(shù)資料
| 型號： | S4503 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS Clock Synthesizer(帶可編程時鐘輸出的BiCMOS時鐘合成器) |
| 中文描述： | BiCMOS工藝時鐘合成器（帶可編程時鐘輸出的BiCMOS工藝時鐘合成器） |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 117K |
| 代理商： | S4503 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 4
S4503
CLOCK SYNTHESIZER
DESCRIPTION OF OPERATION (Refer to
Logic Diagram)
The S4503 synthesizer employs a phase locked loop
(PLL) which includes a “multiplying” counter to produce
a high frequency internal reference oscillator from a
low cost, low frequency crystal. This high frequency
internal reference is the output of a votage controlled
oscillator or VCO. This single VCO frequency is sub
divided down to selectable TTL output frequencies.
One positive (+5V) referenced complementary ECL
(PECL) output (Pout) pair is also provided.
The M counter is a frequency “multiplying” feedback
counter that divides down the VCO frequency, be-
fore applying it to the phase detector. Thus the VCO
frequency is the product of the input reference (crys-
tal) frequency and the M counter modulus. This di-
vide down counter modulus is externally selected to
any integer value from 2 to 32 by a five bit binary
coded value, plus 1, entered into input latches via
the preset input pins M0 through M4. The M0 to M4
inputs have the binary weight of M0=2
0
through
M4=2
4
. The M0-4 inputs are low or 0 if not connected.
NOTE: an entry of all binary zeros will not count down
and is, therefore, invalid. Designs that will load the M
counter inputs from an external register that powers-
up with the outputs in a hi-Z state will need to use
external resistors to ensure the S4503 M counter
inputs are never all zeros.
The output frequency divide down counters “P & T”
each have individual select input pins which may be
actively driven by CMOS/TTL outputs or strapped to
+Vcc (as a 1) or non-connected as appropriate. Non-
connected inputs are biased low or 0. When the bi-
nary coded value of zero is entered into these
counter preselect inputs, their outputs are disabled,
thereby saving AC output power. Note that the input
frequency to the T counter (VCO frequency) is limited
to 250 MHz. P counter will operate up to 300 Mhz.
Output symmetry is very close to 50% duty cycle
with both odd and even division modulus due to an
odd division correction employed at the counter’s
output. Refer to the counter preset tables for the
binary coded preselect input values to division
modulus.
The TTL output drivers of the T counter are source
series terminated by internal resistors of ~40 Ohms
to avoid the need for external termination. This se-
ries termination was choosen to match 50 to 75 Ohm
transmission line traces into end of line load capaci-
tance of ~20 pF. Refer also to the AMCC Clock Driver
Application Note #1. The complementary PECL out-
put emitter followers can source 25 mA from +Vcc
and should be externally terminated at the end of the
transmission line into an equivalent 50 Ohm resis-
tance to +Vcc - 2V.
The analog VCO circuitry requires some external
passive loop filter components mounted very close
to the required S4503 package pins. A VCO fre-
quency centering resistor, RFcenter, is connected
between KVCO and +VCCA, the analog +5V. A fre-
quency span resistor, Rspan, is connected between
pins REXT1 and REXT2. A loop filter series resistor-
capacitor pair, RCOMP & CCOMP is connected be-
tween pin Comp and analog ground GNDA. Note
that the analog ground (GNDA) and +5V (+VCCA)
are to be isolated (decoupled) from the noisier digital
and output power leads VCC and GND.
The input to the XTALIN pin will be a series resonant
crystal of fundamental frequency from 5 to 25 Mhz.
The external addition of series or shunt capacitance to
“pull” the frequency is up to the user’s discretion. An
external series resistor may be required to limit the drive
current from the XTALOUT pin with low ESR crystals.
When the XTALIN pin is driven by an external TTL
clock source, the XTALOUT pin is not connected and
the peak TTL amplitude should not exceed 3 volts. TTL
output signals should be in the range of 5-80 MHz.
System GND
System VCC
VCCA
GNDA
S4503
21
20
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| S450-31 1M SET4+8 | 制造商:RAACO 功能描述:SHELVING BAY SET, 4 SHELVES, 2M HIGH |
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| S4505S/D | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:RAMBUS COMPATIBLE CLOCK GENERATORS |
| S4505S/TD | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:RAMBUS COMPATIBLE CLOCK GENERATORS |
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