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參數(shù)資料
| 型號： | S3C2800 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-BIT RISC MICROPROCESSOR |
| 中文描述： | 32位RISC微處理器 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 119K |
| 代理商： | S3C2800 |
S3C2800 MICROCONTROLLER
DATA SHEET
2
FEATURES
Architecture
· Little-/Big-endian support for external memory.
Address space: 32Mbytes per each bank (Total
256Mbyte)
Supports programmable 8/16/32-bit data bus
width for each memory bank
Fixed bank start address for all (static memory
and dynamic memory banks)
8 memory banks
– 4 memory banks for static memory (ROM,
SRAM, FLASH etc)
– 4 memory banks for dynamic memory (Fast
Page, EDO, and Synchronous DRAM)
Fully programmable access cycles for all static
memory banks
Supports external wait signal to extend the bus
cycle
Supports self-refresh mode in DRAM/SDRAM.
Supports asymmetric/symmetric address of
DRAM
I/D (Instruction/Data) Cache Memory
64-way set-associative ICache (16KB) and
DCache (16KB)
8 words per line with one valid bit and 2 dirty
bits per line
Pseudo-random or round-robin replacement
algorithm
Write-through and Write-back cache operation.
The write buffer can hold 16 words of data and 4
addresses
Low voltage cache for reduced power
consumption
Clock & Power Manager
The on-chip PLL generates the necessary clock
for the operation of MCU at maximum of
200MHz@1.8V
Input frequency range: (Fin) = 6MHz – 10MHz.
Output frequency range: (F
CLK
) = 20MHz –
200MHz
Clock can be selectively provided to each
function block by software
Power Down Mode: NORMAL, SLOW, and IDLE
mode
– NORMAL mode: Normal operating mode
– SLOW mode: Low frequency clock without
PLL
– IDLE mode: Clock to CPU is disabled
PCI Bus Interface
Embedded PCI Host Bridge
32-bit data bus at 66MHz
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