參數(shù)資料
型號: S3C2510A
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example
中文描述: 16/32位RISC微控制器是一種低成本,高性能的微控制器解決方案,以太網為基礎的系統(tǒng),例如,
文件頁數(shù): 7/46頁
文件大?。?/td> 412K
代理商: S3C2510A
S3C2510A
PRODUCT OVERVIEW
1-7
AAL5 SAR and UTOPIA L1/L2
The S3C2510A SAR is a powerful, cost-effective solution for providing packet-to-ATM connectivity. Once a data
packet is given to the S3C2510A SAR, the packet is translated into cells using either the AAL5 protocol or the null
AAL protocol. Then, without further host intervention, the cells are transmitted using selected scheduling
algorithms. The host is notified upon completion of the packet transmission. The S3C2510A SAR also receives
cells from the PHY devices, reassembles them into packets, and notifies the host when a packet has arrived.
All packets are queued in system memory. Misaligned transfers are supported for ease of implementing LANE and
MPOA protocols without requiring any packet data movement. VP scheduling is supported, as well as the more
common VC scheduling, allowing a mix of Permanent Virtual Path (PVP), Switched Virtual Path (SVP), Permanent
Virtual Channel (PVC), and Switched Virtual Channel (SVC) connections.
Some key features are as follow:
— CBR, UBR, rt-VBR and nrt-VBR traffic with rates set on a per-VC or per-VP basis
— AAL0 (raw cells) and AAL5 segmentation and reassembly
— Segments and reassembles data up to about 70Mbps via UTOPIA interface
— Generates and verifies CRC-10 for OAM cells and AAL-3/4 cells
— Concurrent OAM cells and AAL5 cells on each active connection
— Simultaneous segmentation and reassembly of up to 32 connection with internal memory and up to 4K
connection with external memory
— On chip 8K-byte SRAM for internal connection memory
— CAM for connection number mapping (up to 32 connections)
— Packet sizes up to 64K-byte
— Scatter and gather packet capability for large packets
— Starts of Packet offset available for ease of implementing bridging and routing between different protocols
— Big/little endian mode for packet payload
— Glue-less UTOPIA level 2 interface (up to 7 PHYs).
USB Host Controller
S3C2510A supports 2 port USB host interface as follows; Open HCI Rev 1.0 compatible, USB Rev1.1 compatible,
2 down stream ports. Support for Full/Low Speed USB devices. The S3C2510A USB Host controller complies with
OPEN HCI Rev 1.0. Please refer to Open Host Controller Interface Rev 1.0 specification for detail information. The
main features are as follows
— USB specification 1.0 compliant
— Full/Low speed operation support.
— Root hub built in with 2 downstream ports.
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