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參數(shù)資料
| 型號(hào)： | S3924-256Q |
| 廠商： | Hamamatsu Photonics |
| 英文描述： | NMOS linear image sensor Voltage output type with current-integration readout circuit and impedance conversion circuit |
| 中文描述： | NMOS管線性圖像傳感器電壓輸出型電流集成讀出電路和阻抗轉(zhuǎn)換電路 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 244K |
| 代理商： | S3924-256Q |
NMOS linear image sensor
S3921/S3924 series
Figure 2 shows the schematic diagram of the photodiode
active area. This active area has a PN junction consisting of
an N-type diffusion layer formed on a P-type silicon substrate.
A signal charge generated by light input accumulates as a
capacitive charge in this PN junction. The N-type diffusion
layer provides high UV sensitivity but low dark current.
I
Driver circuit
A start pulse
φ
st and 2-phase clock pulses
φ
1,
φ
2 are needed
to drive the shift register. These start and clock pulses are
positive going pulses and CMOS logic compatible.
The 2-phase clock pulses
φ
1,
φ
2 can be either completely
separated or complementary. However, both pulses must not
be
“
High
”
at the same time.
A clock pulse space (X
1
and X
2
in Figure 7) of a
“
rise time/fall
time - 20
”
ns or more should be input if the rise and fall times
of
φ
1,
φ
2 are longer than 20 ns. The
φ
1 and
φ
2 clock pulses
must be held at
“
High
”
at least 200 ns. Since the photodiode
signal is obtained at the rise of each
φ
2 pulse, the clock pulse
frequency will equal the video data rate.
The amplitude of start pulse
φ
st is the same as the
φ
1 and
φ
2
pulses. The shift register starts the scanning at the
“
High
”
level of
φ
st, so the start pulse interval is equal to signal accu-
mulation time. The
φ
st pulse must be held
“
High
”
at least 200
ns and overlap with
φ
2 at least for 200 ns. To operate the shift
register correctly,
φ
2 must change from the
“
High
”
level to the
“
Low
”
level only once during
“
High
”
level of
φ
st. The timing
chart for each pulse is shown in Figure 7.
I
End of scan
The end of scan (EOS) signal appears in synchronization
with the
φ
2 timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
k
resistor.
tvd
tpw
1
tpw
2
tf
s
tr
1
tf
1
X1
X2
t
ov
ts
r-2
tf
2
RESET
Vr
(H)
Vr
(L)
td
r-2
t
ovr
tfr
trr
st
V
s (H)
V
s (L)
V
1 (H)
V
1 (L)
V
2 (H)
V
2 (L)
1
2
END OF SCAN
ACTIVE VIDEO OUTPUT
tpw
s
tr
s
st
1
2
RESET
Figure 7 Timing chart for driver circuit
I
Signal readout circuit
S3921/S3924 series include a current integration circuit uti-
lizing the video line capacitance and an impedance conver-
sion circuit. This allows signal readout with a simple external
circuit. However, a positive bias must be applied to the video
line because the photodiode anode of NMOS linear image
sensors is at 0 V (Vss). This is done by adding an appropriate
pulse to the reset
φ
terminal. The amplitude of the reset pulse
should be equal to
φ
1,
φ
2 and
φ
st.
When the reset pulse is at the high level, the video line is set
at the Reset V voltage. Figure 8 shows the Reset V voltage
margin. A higher clock pulse amplitude allows higher Reset
V voltage and saturation charge. Conversely, if the Reset V
voltage is set at a low level with a higher clock pulse ampli-
tude, the rise and fall times of video output waveform can be
shortened. Setting the Reset V voltage to 2.5 V is recom-
mended when the amplitude of
φ
1,
φ
2,
φ
st and Reset
φ
is 5 V.
To obtain a stable output, an overlap between the reset pulse
(Reset
φ
) and
φ
2 must be settled. (Reset
φ
must rise while
φ
2
is at the high level.) Furthermore, Reset
φ
must fall while
φ
2 is
at the low level.
S3921/S3924 series provide output signals with negative-
going boxcar waveform which include a DC offset of approxi-
mately 1 V when Reset V is 2.5 V. If you want to remove the DC
offset to obtain the positive-going output, the signal readout
circuit and pulse timing shown in Figure 9 are recommended.
In this circuit, Rs must be larger than 10 k
. Also, the gain is
determined by the ratio of Rf to Rs, so choose the Rf value
that suits your application.
Figure 8 Reset V voltage margin
4
0
6
8
10
12
4
5
6
7
8
10
CLOCK PULSE AMPLITUDE (V)
R
2
9
MIN.
RESET
V VOLTAGE
RANGE
MAX.
RECOMMENDED RESET
V VOLTAGE
KMPDC0026EA
KMPDB0047EA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3924-512Q | 制造商:HAMAMATSU 制造商全稱(chēng):Hamamatsu Corporation 功能描述:NMOS linear image sensor Voltage output type with current-integration readout circuit and impedance conversion circuit |
| S3925 | 制造商:Hubbell Premise Wiring 功能描述:Cable Accessories Cover Brass 制造商:Hubbell Wiring Device-Kellems 功能描述:F-BOX CVR, RND, DUP FLAP, BRS |
| S392D | 制造商:VISHAY 制造商全稱(chēng):Vishay Siliconix 功能描述:Silicon PIN Diode |
| S392D_05 | 制造商:VISHAY 制造商全稱(chēng):Vishay Siliconix 功能描述:RF PIN Diode - Dual in SOT-23 |
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