
KSI-8006-003
6
5. Shutdown Techniques
4.7K
1
COMP
Shutdown of the S3842 can be
V
REF
accomplished by two methods;
3
I
4.7K
5.00
either raise pin3 above 1V or pull
pin1 below a voltage two diodes
DOW N
drops above ground. Either causes
the output of the PWM method
comparator to be high (refer to
block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after
the shutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be
accomplished by adding an SCR which turn off, allowing the SCR to reset.
6. Open Loop Test
High peak currents associated with capacitive leads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Pin5 in a single point ground. The transistor and 5
potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to Pin3.
7. Slope Compensation
A fraction of the oscillator ramp can be resistively
V
summed with the current sense signal to provide
slope compensation for converters requiring duty
cycle over 50%. Note that capacitor C, forms a
4
R
T
/C
/C
T
R
filter with R
2
to suppress the leading edge switch
spikes.
3
I
SENSE
C
R
SENSE
0.1uF
S3842
8
SENSE
SHUT
SHUT
I
SENSE
ADJUST
S3842
V
REF
1
GND
V
REF
I
SENSE
4.7K
COMP
2
3
4
8
7
6
5
Vcc
OUTPUT
GROUND
ERROR
AMP
ADJUST
2N2222
R
T
4.7K
1K
0.1uF
0.1uF
1K/1W
R
T
/C
T
Vin
Vcc
OUTPUT
100K