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參數(shù)資料
| 型號： | S374 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS |
| 中文描述： | 八路D型透明鎖存器和邊沿觸發(fā)觸發(fā)器 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 685K |
| 代理商： | S374 |
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SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B
–
OCTOBER 1975
–
REVISED AUGUST 2002
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VIL
VIK
2
V
0.8
V
VCC = MIN,
II =
–
18 mA
–
1.2
V
VOH
SN54S
’
SN74S
’
VCC= MIN
VCC = MIN,
VIH= 2 V
VIH = 2 V,
VIL= 0 8 V
VIL = 0.8 V,
IOH= MAX
IOH = MAX
2.4
3.4
V
2.4
3.1
VOL
IOZH
IOZL
II
IIH
IIL
IOS
§
VCC = MIN,
VCC = MAX,
VCC = MAX,
VCC = MAX,
VCC = MAX,
VCC = MAX,
VCC = MAX
VIH = 2 V,
VIH = 2 V,
VIH = 2 V,
VI = 5.5 V
VI = 2.7 V
VI = 0.5 V
VIL = 0.8 V,
VO = 2.4 V
VO = 0.5 V
IOL = 20 mA
0.5
V
50
A
–
50
A
1
mA
50
A
–
250
A
–
40
–
100
mA
Outputs high
160
’
S373
Outputs low
160
Outputs disabled
190
ICC
VCC = MAX
Outputs high
110
mA
’
S374
Outputs low
140
Outputs disabled
160
CLK and OC at 4 V, D inputs at 0 V
180
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC= 5 V, TA = 25
°
C.
§
Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
switching characteristics, V
CC
= 5 V, T
A
= 25
°
C (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
TEST CONDITIONS
’
S373
TYP
’
S374
TYP
UNIT
(OUTPUT)
MIN
MAX
MIN
MAX
fmax
RL = 280
CL = 15 pF,
See Note 3
75
100
MHz
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Data
Any Q
RL = 280
CL
See Note 3
7
12
ns
,
7
12
C or CLK
Any Q
RL = 280
CL
See Note 3
7
14
8
15
ns
,
12
18
11
17
OC
Any Q
RL = 280
CL
See Note 3
8
15
8
15
ns
,
11
18
11
18
OC
Any Q
RL= 280
CL= 5 pF
RL = 280
CL = 5 pF
6
9
5
9
ns
8
12
7
12
NOTE 3. Maximum clock frequency is tested with all outputs loaded.
fmax= maximum clock frequency
tPLH= propagation delay time, low-to-high-level output
tPHL= propagation delay time, high-to-low-level output
tPZH= output enable time to high level
tPZL= output enable time to low level
tPHZ= output disable time from high level
tPLZ= output disable time from low level
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