參數(shù)資料
型號(hào)： S3064
廠商： Applied Micro Circuits Corp.
英文描述： SONET/SDH/ATM OC-48 Differential 1：16 Receiver(SONET/SDH/ATM差分1：16接收器)
中文描述： 的SONET / SDH / ATM的OC - 48用差分1:16接收器（的SONET / SDH / ATM的差分1:16接收器）
文件頁(yè)數(shù)： 4/21頁(yè)
文件大?。?/td> 155K
代理商： S3064
S3064
SONET/SDH/ATM OC-48 DIFFERENTIAL 1:16 RECEIVER
4
December 6, 1999 / Revision NC
RECEIVER OPERATION
The S3064 receiver chip provides the first stage of
digital processing of a receive SONET STS-48 bit-
serial stream. It converts the bit-serial 2.488 Gbps
data stream into a 155.52 Mbyte/sec parallel data
format. A loopback mode is provided for diagnostic
loopback (transmitter to receiver). A Line Loopback
(receiver to transmitter) is also provided.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by one A2 byte. Framing
pattern detection is enabled and disabled by the
FRAMEN input. Detection is enabled by a rising edge
on OOF when FRAMEN is active. It is disabled when
a framing pattern is detected. When framing pattern
detection is enabled, the framing pattern is used to
locate byte and frame boundaries in the incoming data
stream (RSD or looped transmitter data). During this
time, the parallel data bus (POUTP/N[15:0]) will not
contain valid data. The timing generator block takes
the located byte boundary and uses it to block the
incoming data stream into bytes for output on the
parallel output data bus (POUTP/N[15:0]). The frame
boundary is reported on the frame pulse (FP) output
when any 32-bit pattern matching the framing pat-
tern is detected on the incoming data stream. When
framing pattern detection is disabled, the byte bound-
ary is frozen to the location found when detection
was previously enabled. Only framing patterns
aligned to the fixed byte boundary are indicated on
the FP output.
The probability that random data in an STS-48
stream will generate the 32-bit framing pattern is ex-
tremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
μ
s, even for extremely high bit error
rates.
Serial to Parallel Converter
The serial to parallel converter consists of three
16-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial to parallel con-
version. The second is an 16-bit internal holding
register, which transfers data from the serial to par-
allel register on byte boundaries as determined by
the frame and byte boundary detection block. On the
falling edge of the free running POCLK, the data in
the holding register is transferred to an output hold-
ing register which drives POUTP/N[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for diag-
nostic purposes. The differential serial output clock
and data from the transmitter (LSCLK and LSD) is
routed to the serial-to-parallel block in place of the
normal data stream (RSCLK and RSD). When DLEB
is asserted, SDPECL shall be ignored.
Line Loopback
The Line Loopback circuitry consists of alternate
clock and data output drivers. When LLEB is active,
it enables the Line Loopback output data and clock
(LLD and LLCLK) and a receive-to-transmit loopback
can be established at the serial data rate.
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