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| 型號(hào)： | S3063 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-48 Differential 16:1 Transmitter(SONET/SDH/ATM差分16選1傳送器) |
| 中文描述： | 的SONET / SDH / ATM的OC - 48用差分16:1發(fā)射器（的SONET / SDH / ATM的差分16選1傳送器） |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 53K |
| 代理商： | S3063 |
3
OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC
September 27, 1999
Theory Of Operation
1. The S3040 extracts the clock and re-times the
data from the received differential PECL serial
data input (SERDATIP/N) coming from the fiber
optic receiver when the signal detect (SDN) is a
PECL Low level. When signal detect (SDN) is at a
PECL High level, the Phase Lock Loop (PLL) will
be forced to lock to the PECL Reference Clock
(REFCLKP/N). When the transmit PLL is locked
to the reference clock input the lock detect
(LOCKDET) TTL output goes High.
2. The S3064 receives the OC-48 (2.488 Gbit/s)
scrambled NRZ data signals on the serial data
stream (RSDP/N) LVPECL inputs. These inputs
are clocked into the S3064 by the Receive Serial
Clock (RSCLKP/N) LVPECL inputs. This clock is
used by the receive section as the master clock
to perform framing and deserialization functions.
3. When FRAMEN is disabled [FRAMEN = 0] and
OOF is connected to ground, the Frame Pulse
(FP) output is always inactive. The AMAZON de-
vice should be in default mode [RX_FRMR_INH =
0]. In this mode, the parallel input data is not
assumed to be byte aligned. The AMAZON de-
vice will align to the incoming data.
4. The serial-bit data stream is then converted into a
16-bit parallel data format for output onto the dif-
ferential parallel output data bus (POUTP/
N[15:0]). The differential 16-bit parallel data is
clocked out of the S3064 and into the AMCC/
Cimaron AMAZON S4801 with the differential
Parallel Output Clock (POCLK).
5. The 16-bit parallel data is output from the AMCC/
Cimaron AMAZON S4801 into the S3063 differ-
ential parallel data input bus (PIN[15:0]) and is
sampled by the Parallel Input Clock (PICLK) of
the S3063. This clock is generated by the S3063
Parallel Clock (PCLK) which is fed into the
AMCC/Cimaron AMAZON S4801 as the transmit
clock (TX_SONETCLK) and then back into the
PICLK input of the S3063.
6. The 16-bit parallel data is then converted to bit-
serial data and output through the Transmit Serial
Data (TSDP/N) connections to the Sumitomo fiber
optic transmitter (SDM7128-XC).
7. If the incoming serial-bit data stream is lost (when
SDN is High) the lock detect circuit internal to the
S3040 substitutes the external reference clock for
the missing data stream clocking signal. This sub-
stitution of reference timing source is helpful to
supply a continuous timing signal for the up-
stream devices and system operation even
though valid received data does not exist. This
switch over is a smooth transition with no notice-
able phase shift.
Parts List
The following is a parts list that is a recommendation to the designer to implement the circuit in Figures 1 and 2.
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