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參數(shù)資料
| 型號(hào)： | S3062 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC |
| 中文描述： | 多速率（OC-48/24/12/3/GBE/FC）的SONET / SDH / ATM的收發(fā)器瓦特/前向糾錯(cuò) |
| 文件頁(yè)數(shù)： | 5/27頁(yè) |
| 文件大?。?/td> | 308K |
| 代理商： | S3062 |
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5
S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
September 17, 2002/ Revision A
Figure 5. Clock Synthesizer
M
N
PD
LPF
VCO
VCOCLK
REFCLK
FECSEL (0-1)
FECSEL 2
RSCLK
Where N = 14/15/16/17
M = 14/15/16/17
RSCLK =
VCOCLK M
RSCLK Divider
VCO Divider
A high on FECSEL2 selects RSCLK divided by N. A
low on FECSEL2 selects the REFCLK. The REFCLK
or RSCLK divided by N is divided by 1/M (multiplied
by M) in the loop. The value of M and N can be
selected by FECSEL0 and FECSEL1.
When FECSEL2 = 0, VCOCLK = REFCLK * M. The
user must select the proper value of REFCLK and M
to get the desired VCOCLK frequency. When
FECSEL2 = 1, VCOCLK = (RSCLK * M)
÷
N. The
user must select the proper M/N ratio (with
FECSEL0 and FECSEL1) to get the desired
VCOCLK value. (See Tables 3 and 4.)
Example: OC-48 FEC capability of 8 bytes per
255-byte block. Required VCOCLK = 2.6656 GHz.
Method 1:
Required VCOCLK = 2.6656 GHz
FECSEL2 = 0, selects REFCLK
FECSEL0 = 1 and FECSEL1 = 0, selects VCO
divider(M) = 16
REFCLK = 2.6656 GHz
÷
16 = 166.60 MHz
VCOCLK = REFCLK
÷
(1/M) = 166.60 * 16 = 2.6656
GHz
Method 2:
Required VCOCLK = 2.6656 GHz
FECSEL2 = 1, selects RSCLK
FECSEL0 = 0 and FECSEL1 = 0, selects VCO
divider(M) = 17 and RSCLK divider(N) = 16
RSCLK = (2.6656 * 16)
÷
17 = 2.5088 GHz
VCOCLK = RSCLK
÷
N
÷
(1/M) = 2.5088 GHz
÷
16 *
17 = 2.6656 GHz.
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