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參數(shù)資料
| 型號： | S3040A |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復(fù)單元) |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP32 |
| 封裝： | HEAT SINK, TQFP-32 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大?。?/td> | 117K |
| 代理商： | S3040A |
S3040A
SONET/SDH CLOCK RECOVERY UNIT
4
April 4, 2000 / Revision D
Figure 3. Input Jitter Tolerance Specification
Figure 4. Jitter Transfer Specification
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
f0
Frequency
f1
f2
f3
ft
0.4
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
OC/STS
Level
f0
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
f1
(Hz)
48
10
600
6000
100
1000
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
CHARACTERISTICS
Performance
The S3040 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed 0.01 UI rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 3).
OC/STS
Level
48
1,2
fc
(MHz)
P
(dB)
2
0.1
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