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參數(shù)資料
| 型號： | S3040 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OC-48 Clock Recovery Unit(OC-48時鐘恢復(fù)單元) |
| 中文描述： | CLOCK RECOVERY CIRCUIT, CQCC28 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 78K |
| 代理商： | S3040 |
3
EV3040
OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD
August 13, 1999
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Table 1. Power Connections for DUT and Test Equipment Interface
SMA Connectors
SMA connectors are provided for the differential serial data input/output signals and output clock.
Serial Data In [SERDATIP/N]
– PECL Differential inputs. Clock is recovered from the transition on these inputs.
Reference Clock [REFCLKP/N]
– PECL Differential inputs. These inputs are used to establish the initial
operating frequency of the clock recovery PLL and are also used as a standby clock in the absence of data.
These inputs must be provided with a differential clock of 155.52 MHz.
Serial Data Out [SERDATOP/N]
– CML outputs. This signal is the delayed version of the incoming data stream
(SERDATI) updated on the falling edge of Serial Clock Out (SERCLKOP).
Serial Clock Output [SERCLKP/N]
– CML outputs. This signal is phase aligned with Serial Data Out
(SERDATOP).
Lock Detect [LOCKDET]
– TTL output. Indicates that the Clock Recovery Unit (CRU) has locked onto the
incoming data stream.
DIP Switches
The evaluation board is equipped with a DIP switch to control the static control functions of the on-board device.
For both arrays the OFF (open = “0”) condition of the DIP switch asserts a logic low on the assigned signal, and
the ON (closed = “1”) condition asserts a logic high. Figure 2 shows the particular DIP switch settings that are
needed for a particular test case.
Lock to Reference [LCKREFN]
– Active Low. When active, the serial clock output will be forced to lock to the
local reference clock input [REFCLK].
Signal Detect [SDN]
– Active Low. Used to indicate a loss of received optical power.
Bypass Enable [BYPASS]
– Active High. Used to bypass the VCO in the PLL.
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