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參數(shù)資料
| 型號： | S3028 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver(帶片上鎖相環(huán)，頻率可選的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | 的SONET / SDH / ATM的OC-3/12收發(fā)器（帶片上鎖相環(huán)，頻率可選的的SONET / SDH收發(fā)器（完全集成OC-3/12接口器件）） |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 167K |
| 代理商： | S3028 |
16
S3028
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
December 13, 1999 / Revision H
Table 14. AC Receiver Timing Characteristics
Figure 7. Receiver Output Timing
Notes on TTL Output Timing:
1. Output propagation delay time of TTL outputs is the time in nanoseconds from the 50%
point of the reference signal to the 30% or 70% point of the output.
2. Maximum output propagation delays and duty cycles of TTL outputs are measured with a
15 pF load.
3. When a set-up time is specified on TTL signals between an output and a clock, the set-up
time is the time in nano seconds from the 50% point of the output to the 50% point of the clock.
4. When a hold time is specified on TTL signals between an output and a clock, the hold time
is the time in nano seconds from the 50% point of the clock to the 50% point of the output.
POUT[7:0], FP
POCLK
tHPOUT
tPPOUT
MIN
tPPOUT
MAX
50%
tSPOUT
tHPOUT
Duty Cycle MIN
Duty Cycle MAX
tPPOUT
70%
30%
MIN
Figure 8. Receiver Input Timing
RSD
tS
RSD
tH
RSCLKP
RSDP/N
Notes on High-Speed PECL Input Timing
1.Timing is measured from the cross-over point of the reference signal to the cross-over
point of the input.
1. Set-up and hold times are specified for an interface which directly connects the S3028 receiver parallel outputs to the data and
clock inputs on an external register.
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