- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374664 > S3025 (APPLIEDMICRO INC) SONET/SDH/ATM Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH/ATM時鐘恢復(fù)單元) PDF資料下載
參數(shù)資料
| 型號： | S3025 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH/ATM時鐘恢復(fù)單元) |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQCC16 |
| 封裝： | PLASTIC, LCC-16 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | S3025 |
3
S3025
SONET/SDH/ATM CLOCK RECOVERY UNIT
OVERVIEW
The S3025 supports clock recovery for the OC-12/
STM-4 data rate. Differential serial data is input to the
chip at the specified rate and clock recovery is per-
formed on the incoming data stream. An external
crystal is required to minimize the PLL lock time and
provide a stable output clock source in the absence of
serial input data. Retimed data and clock are output
from the S3025.
CHARACTERISTICS
Performance
The S3025 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
T1X1.6/91-022 document, when used with differential
inputs and outputs as shown in Figure 3.
Jitter Transfer
Jitter transfer functions is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 5.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 4 be applied for
each of the OC-N/STS-N rates.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 4. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed .01 U.I. when a serial data input with
less than 14ps rms jitter is presented to the serial
data inputs.
Figure 3. Clock Output to Data Transition Delay
Output Frequency
622.08 MHz
SERDATOP/N Setup Time
450 ps
SERDATOP/N Hold Time
450 ps
tsu
th
SERCLKOP/N
SERDATOP/N
Figure 4. Input Jitter Tolerance Specification
f0
f1
f2
f3
ft
.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
Frequency
OC/STS
Level
f0
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
f1
(Hz)
12
10
30
300
25
250
Figure 5. Jitter Transfer Specification
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
OC/STS
Level
12
1,2
fc
(kHz)
P
(dB)
500
0.1
1. Bellcore Specifications: TR-NWT-000253, Issue 2,
December 1991.
2. CCITT Recommendations: G.958.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S3026 | SONET/SDH/ATM Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH/ATM時鐘恢復(fù)單元) |
| S3027 | SONET/SDH/ATM Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH/ATM時鐘恢復(fù)單元) |
| S3028 | SONET/SDH/ATM OC-3/12 Transceiver(帶片上鎖相環(huán)，頻率可選的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| S3029 | Clock Synthesis and Recovery Unit(數(shù)據(jù)傳送速率155 MBit/S的時鐘合成和恢復(fù)單元) |
| S302H | S302H |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3028 | 制造商:ASI 制造商全稱:ASI 功能描述:SILICON ABRUPT VARACTOR DIODE |
| S3029 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER |
| S3029A | 制造商:AppliedMicro 功能描述: |
| S302AB | 制造商:Cinch Connectors 功能描述:Conn Wire to Board SKT 2 POS Solder Lug ST Panel Mount |
| S-302-AB | 功能描述:Jones 插頭和插槽 2C PNL MNT SOCKET RoHS:否 制造商:Molex 產(chǎn)品類型:Socket Connectors 系列:Beau 位置/觸點數(shù)量:8 電壓額定值:250 V 電流額定值:10 A 外殼材料:Thermoplastic 觸點材料:Phosphor Bronze 觸點電鍍:Tin-Lead |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。