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參數(shù)資料
| 型號： | S3023 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM Clock Recovery Unit(SONET/SDH/ATM時鐘恢復單元) |
| 中文描述： | 的SONET / SDH / ATM的時鐘恢復單元（的SONET / SDH / ATM的時鐘恢復單元） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 202K |
| 代理商： | S3023 |
3
S3023
SONET/SDH/ATM CLOCK RECOVERY UNIT
April 10, 2001 / Revision A
OVERVIEW
The S3023 supports clock recovery for the OC-12/
STM-4 or OC-3/STM-1 data rates. Differential serial
data is input to the chip at the specified rate and
clock recovery is performed on the incoming data
stream. An external crystal is required to minimize
the PLL lock time and provide a stable output clock
source in the absence of serial input data. Retimed
data and clock are output from the S3023.
CHARACTERISTICS
Performance
The S3023 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
T1X1.6/91-022 document, when used with differential
inputs and outputs as shown in Figure 3.
Jitter Transfer
The jitter transfer function is defined as the ratio of
jitter on the output OC-N/STS-N signal to the jitter
applied on the input OC-N/STS-N signal versus fre-
quency. Jitter transfer requirements are shown in
Figure 5. The measurement condition is that input
sinusoidal jitter up to the mask level in Figure 4 be
applied for each of the OC-N/STS-N rates.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 4. The measurement
condition is the input jitter amplitude which causes an
equivalent of 1 dB power penalty.
Serial Data Output Set-up and Hold Time
The output set-up and hold times are represented by
the waveforms shown in Figure 3.
Jitter Generation
The jitter generation of the serial clock and serial
data outputs shall not exceed 0.01 UI when a serial
data input with less than 14ps (OC-12) or 56ps (OC-
3) rms jitter is presented to the serial data inputs.
Figure 3. Clock Output to Data Transition Delay
Output Frequency
622.08 MHz
155.52 MHz
SERDATOP/N Setup Time
450 ps
2.5 ns
SERDATOP/N Hold Time
450 ps
2.5 ns
tS
tH
SERCLKOP
SERDATOP/N
Figure 4. Input Jitter Tolerance Specification
f0
Frequency
f1
f2
f3
ft
0.15
1.5
15
Sinusodal
Input Jitter
Amplitude
(UI p-p)
OC/STS
Level
f0
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
f1
(Hz)
12
10
30
300
25
250
3
10
30
300
6.5
65
Figure 5. Jitter Transfer Specification
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/decade
OC/STS
Level
12
1,2
fc
(kHz)
P
(dB)
500
0.1
3
1,2
130
0.1
1. Bellcore Specifications: TR-NWT-000253, Issue 2,
December 1991.
2. CCITT Recommendations: G.958.
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