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| 型號： | S29PL127N65GFI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| 中文描述： | 8M X 16 FLASH 3V PROM, 65 ns, PBGA64 |
| 封裝： | 8 X 11.60 MM, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 23/85頁 |
| 文件大?。?/td> | 940K |
| 代理商： | S29PL127N65GFI003 |
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November 23, 2005 S29PL-N_00_A4
S29PL-N MirrorBit Flash Family
21
P r e l i m i n a r y
7
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset
features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see
Table 12.1
and
Table 12.2
). The command regis-
ter itself does not occupy any addressable memory location. Instead, the command register is
composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as input to the internal state
machine and the state machine outputs dictate the function of the device. Writing incorrect ad-
dress and data values or writing them in an improper sequence can place the device in an
unknown state, in which case the system must write the reset command to return the device to
the reading array data mode.
7.1
Device Operation Table
The device must be setup appropriately for each operation.
Table 7.1
describes the required state
of each control pin for any particular operation.
Legend:
L = Logic Low = V
, H = Logic High = V
IH
, V
HH
= 8.5 – 9.5 V, X = Don’t Care, SA = Sector Address, A
IN
= Address
In, D
IN
= Data In, D
OUT
= Data Out
Note:
WP#/ACC must be high when writing to upper two and lower two sectors (PL256N: 0, 1,132, and 133; PL127/129N:
0, 1, 68, and 69)
7.1.1 Dual Chip Enable Device Description and Operation ( PL129N Only)
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate pro-
cessors with a limited addressable range. This product operates as two separate devices in a
single package and requires the processor to address half of the memory space with one chip en-
able and the remaining memory space with a second chip enable. For more details on the
addressing features of the Dual CE# device refer to
Table 6.3 on page 20
for the PL129N Sector
and Memory Address Map.
Dual chip enable products must be setup appropriately for each operation. To place the device
into the active state either CE1# or CE2# must be set to V
IL
. To place the device in standby mode,
both CE1# and CE2# must be set to V
IH
.
Table 7.2
describes the required state of each control
pin for any particular operation.
Table 7.1 Device Operation
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(A
max
– A0)
DQ15 – DQ0
Read
L
L
H
H
X
A
IN
D
OUT
Write
L
H
L
H
X
(
See Note
)
A
IN
D
IN
Standby
H
X
X
H
X
A
IN
High-Z
Output Disable
L
H
H
H
X
A
IN
High-Z
Reset
X
X
X
L
X
A
IN
High-Z
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| S29PL127N65GFIW00 | 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29PL127N65GFIW00 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL127N65GFIW02 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL127N65GFIW03 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL127N65GFW000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
| S29PL127N65GFW002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory |
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