參數(shù)資料
型號： S29PL127J55
廠商： Spansion Inc.
英文描述： CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： 3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶
文件頁數(shù)： 6/106頁
文件大小： 1997K
代理商： S29PL127J55
4
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A62 April 7, 2005
P R E L I M I N A R Y
General Description
The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page
Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2
Mwords. The devices are offered in the following packages:
11mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J and PL129J)
8mm
x
11.6mm,
64-ball
Fine-pitch
(PL127J/PL129J)
8.15mm x 6.15mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)
7mm x 9mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and
PL032J)
20mm x 14mm, 56-pin TSOP (PL127J)
The word-wide data (x16) appears on DQ15-DQ0. This device can be pro-
grammed in-system or in standard EPROM programmers. A 12.0 V V
PP
is not
required for write or erase operations.
BGA
multi-chip
compatible
The device offers fast page access times of 20 to 30 ns, with corresponding ran-
dom access times of 55 to 70 ns, respectively, allowing high speed
microprocessors to operate without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Bank
PL127J Sectors
PL064J Sectors
PL032J Sectors
A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
4 Mbit (4 Kw x 8 and 32 Kw x 7)
B
48 Mbit (32 Kw x 96)
24 Mbit (32 Kw x 48)
12 Mbit (32 Kw x 24)
C
48 Mbit (32 Kw x 96)
24 Mbit (32 Kw x 48)
12 Mbit (32 Kw x 24)
D
16 Mbit (4 Kw x 8 and 32 Kw x 31)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
4 Mbit (4 Kw x 8 and 32 Kw x 7)
Bank
PL129J Sectors
CE# Control
1A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE1#
1B
48 Mbit (32 Kw x 96)
CE1#
2A
48 Mbit (32 Kw x 96)
CE2#
2B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE2#
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL127J60 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
S29PL127J60BAI000 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 60NS 80FBGA - Bulk
S29PL127J60BFI000 制造商:Spansion 功能描述:FLASH PARALLEL - Bulk
S29PL127J60TAI130 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 128MBIT 8MX16 60NS 56TSOP - Trays
S29PL127J60TFI130 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 128M-Bit 8M x 16 60ns 56-Pin TSOP Tray
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