參數(shù)資料
型號(hào)： S29PL032J70BAW13
廠(chǎng)商： SPANSION LLC
元件分類(lèi)： PROM
英文描述： 2M X 16 FLASH 3V PROM, 70 ns, PBGA56
封裝： 7 X 9 MM, FBGA-56
文件頁(yè)數(shù)： 18/100頁(yè)
文件大?。?/td> 967K
代理商： S29PL032J70BAW13
24
S29PL127J/S29PL129J/S29PL064J/S29PL032J
31107A5 March 15, 2004
P R EL IMINAR Y
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of tREADY (during Embedded Algorithms). The system can thus monitor
RY/BY# to determine whether the reset operation is complete. If RESET# is as-
serted when a program or erase operation is not executing (RY/BY# pin is “1”),
the reset operation is completed within a time of tREADY (not during Embedded Al-
gorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the "AC Characteristic" section tables for RESET# parameters and to 13
for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins
(except for RY/BY#) are placed in the highest Impedance state
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