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  • 參數(shù)資料
    型號(hào): S29PL-J70BFI013
    廠商: Spansion Inc.
    元件分類: DRAM
    英文描述: CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
    中文描述: CMOS 3V電壓供電,同步讀/寫Flash存儲(chǔ)器并有增強(qiáng)VersatileIO控制
    文件頁數(shù): 70/96頁
    文件大小: 827K
    代理商: S29PL-J70BFI013
    68
    S29PL-J
    S29PL-J_00_A9 September 22, 2006
    D a t a
    S h e e t
    ( A d v a n c e
    I n f o r m a t i o n )
    16.7
    DQ3: Sector Erase Timer
    After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
    erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
    are selected for erasure, the entire time-out also applies after each additional sector erase command. When
    the time-out period is complete, DQ3 switches from a “0” to a “1.” See also the
    Sector Erase Command
    Sequence
    on page 59
    .
    After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
    (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is
    “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
    until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands.
    To ensure the command has been accepted, the system software should check the status of DQ3 prior to and
    following each subsequent sector erase command. If DQ3 is high on the second status check, the last
    command might not have been accepted.
    Table 16.1
    shows the status of DQ3 relative to the other status bits.
    Notes:
    1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to
    DQ5:
    Exceeded Timing Limits on page 67
    for more information.
    2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
    3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in
    progress. The device outputs array data if the system addresses a non-busy bank.
    Table 16.1
    Write Operation Status
    Status
    DQ7
    (Note 2)
    DQ6
    DQ5
    (Note 1)
    DQ3
    DQ2
    (Note 2)
    RY/BY#
    Standard
    Mode
    Embedded Program
    Algorithm
    DQ7#
    Toggle
    0
    N/A
    No toggle
    0
    Embedded Erase
    Algorithm
    0
    Toggle
    0
    1
    Toggle
    0
    Erase
    Suspend
    Mode
    Erase
    Suspend-
    Read
    Erase
    Suspended
    Sector
    1
    No toggle
    0
    N/A
    Toggle
    1
    Non-Erase
    Suspended
    Sector
    Data
    Data
    Data
    Data
    Data
    1
    Erase-Suspend
    -Program
    DQ7#
    Toggle
    0
    N/A
    N/A
    0
    Program
    Suspend
    Mode
    (Note 3)
    Reading within
    Program
    Suspended Sector
    Invalid
    (Not Allowed)
    Invalid
    (Not Allowed)
    Invalid
    (Not Allowed)
    Invalid
    (Not Allowed)
    Invalid
    (Not Allowed)
    1
    Reading within
    Non-program
    Suspended Sector
    Data
    Data
    Data
    Data
    Data
    1
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