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| 型號： | S29PL-J55BFI022 |
| 廠商： | Spansion Inc. |
| 元件分類： | DRAM |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | CMOS 3V電壓供電，同步讀/寫Flash存儲器并有增強VersatileIO控制 |
| 文件頁數(shù)： | 78/96頁 |
| 文件大?。?/td> | 827K |
| 代理商： | S29PL-J55BFI022 |
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76
S29PL-J
S29PL-J_00_A9 September 22, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
20.6
Erase/Program Operations
Notes:
1. Not 100% tested.
2. S29PL129J - During CE1# transitions, CE2# = V
IH
; During CE2# transitions, CE1# = V
IH
3. S29PL129J - There are two CE# (CE1#, CE2#).
4. See
Table 21.4 on page 84
for more information.
Table 20.5
Erase and Program Operations
Parameter
Description
Speed Options (ns)
JEDEC
Std
55
60
65
70
Unit
t
AVAV
t
AVWL
t
WC
t
AS
t
ASO
t
AH
Write Cycle Time
(Note 1)
Min
55
60
65
70
Address Setup Time
Min
0
ns
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
t
WLAX
Address Hold Time
Min
30
35
ns
t
AHT
Address Hold Time From CE# (CE1#, CE#2 in PL129J) or OE# high during
toggle bit polling
Min
0
ns
t
DVWH
t
WHDX
t
DS
t
DH
t
OEPH
Data Setup Time
Min
25
30
ns
Data Hold Time
Min
0
ns
Output Enable High during toggle bit polling
Min
10
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
WHEH
t
WLWH
t
WHDL
t
CS
t
CH
t
WP
t
WPH
t
SR/W
t
WHW
H1
t
WHW
H1
t
WHW
H2
t
VCS
t
RB
CE# (CE1# or CE#2 in PL129J) Setup Time
Min
0
ns
CE# (CE1# or CE#2 in PL129J) Hold Time
Min
0
ns
Write Pulse Width
Min
35
ns
Write Pulse Width High
Min
20
25
ns
Latency Between Read and Write Operations
Min
0
ns
t
WHWH
1
t
WHWH
1
t
WHWH
2
Programming Operation
(Note 4)
Typ
6
μs
Accelerated Programming Operation
(Note 4)
Typ
4
μs
Sector Erase Operation
(Note 4)
Typ
0.5
sec
V
CC
Setup Time
(Note 1)
Min
50
μs
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
Min
35
ns
t
PSL
t
ESL
Program Suspend Latency
Max
35
μs
Erase Suspend Latency
Max
35
μs
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