參數(shù)資料
型號： S29PL-J55BAW023
廠商： Spansion Inc.
元件分類： DRAM
英文描述： CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： CMOS 3V電壓供電，同步讀/寫Flash存儲器并有增強VersatileIO控制
文件頁數(shù)： 66/96頁
文件大小： 827K
代理商： S29PL-J55BAW023
64
S29PL-J
S29PL-J_00_A9 September 22, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except
where BA is required) and data bits higher than DQ7 are don’t cares.
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6,
program command must be issued and verified again.
7. Data is latched on the rising edge of WE#.
8. Entire command sequence must be entered for each portion of password.
9. Command sequence returns FFh if PPMLB is set.
10.The password is written over four consecutive cycles, at addresses 0-3.
11.A 2 μs timeout is required between any two portions of password.
12.A 100 μs timeout is required between cycles 4 and 5.
13.A 1.2 ms timeout is required between cycles 4 and 5.
14.Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must
be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure.
15.DQ1 = 1 if PPB locked, 0 if unlocked.
16.Once the Secured Silicon Sector Entry Command sequence has been entered, the standard array cannot be accessed until the Exit
SecSi Sector command has been entered or the device has been reset.
16. Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7.
Table 16.1 on page 68
and the following subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether a program or erase operation is complete or in
progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an
Embedded Program or Erase operation is in progress or has been completed.
16.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 μs, then that bank returns to the read
mode.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 400 μs, then the bank returns to the read mode. If not all selected sectors
are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the
status may not be valid.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at
DQ15–DQ0 on the
following
read cycles. Just prior to the completion of an Embedded Program or Erase
operation, DQ7 may change asynchronously with DQ15–DQ0 while Output Enable (OE#) is asserted low.
That is, the device may change from providing status information to valid data on DQ7. Depending on when
the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed
the program or erase operation and DQ7 has valid data, the data outputs on DQ15–DQ0 may be still invalid.
Valid data on DQ15–DQ0 will appear on successive read cycles.
Table 16.1 on page 68
shows the outputs for Data# Polling on DQ7.
Figure 16.1 on page 65
shows the
Data# Polling algorithm.
Figure 20.10 on page 79
shows the Data# Polling timing diagram.
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