- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365401 > S29PL-J55BAW022 (Spansion Inc.) CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control PDF資料下載
參數(shù)資料
| 型號： | S29PL-J55BAW022 |
| 廠商： | Spansion Inc. |
| 元件分類： | DRAM |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | CMOS 3V電壓供電，同步讀/寫Flash存儲器并有增強VersatileIO控制 |
| 文件頁數(shù)： | 25/96頁 |
| 文件大?。?/td> | 827K |
| 代理商： | S29PL-J55BAW022 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
September 22, 2006 S29PL-J_00_A9
S29PL-J
23
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
10.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+ 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Note that during
automatic sleep mode, OE# must be at V
IH
before the device reduces current to the stated sleep mode
specification. ICC5 in
DC Characteristics
on page 71
represents the automatic sleep mode current
specification.
10.6
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP
, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held at V
IL
but not within V
SS
±0.3 V, the standby current
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is
completed within a time of t
READY
(not during Embedded Algorithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to the tables in
AC Characteristic
on page 72
for RESET# parameters and to
Figure 20.5 on page 75
for the timing diagram.
10.7
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The output pins (except for RY/BY#) are
placed in the highest Impedance state
Table 10.5
PL127J Sector Architecture (Sheet 1 of 7)
Bank
Sector
Sector Address (A22-A12)
Sector Size (Kwords)
Address Range (x16)
B
SA0
00000000000
4
000000h–000FFFh
SA1
00000000001
4
001000h–001FFFh
SA2
00000000010
4
002000h–002FFFh
SA3
00000000011
4
003000h–003FFFh
SA4
00000000100
4
004000h–004FFFh
SA5
00000000101
4
005000h–005FFFh
SA6
00000000110
4
006000h–006FFFh
SA7
00000000111
4
007000h–007FFFh
SA8
00000001XXX
32
008000h–00FFFFh
SA9
00000010XXX
32
010000h–017FFFh
SA10
00000011XXX
32
018000h–01FFFFh
SA11
00000100XXX
32
020000h–027FFFh
SA12
00000101XXX
32
028000h–02FFFFh
SA13
00000110XXX
32
030000h–037FFFh
SA14
00000111XXX
32
038000h–03FFFFh
SA15
00001000XXX
32
040000h–047FFFh
SA16
00001001XXX
32
048000h–04FFFFh
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29PL-J55BAW023 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI000 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI001 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI002 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI003 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29PL-J55BAW023 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI001 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J55BFI003 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。