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參數(shù)資料
| 型號： | S29GL128P11FFI022 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 128M X 1 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 55/71頁 |
| 文件大?。?/td> | 990K |
| 代理商： | S29GL128P11FFI022 |
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November21,2006 S29GL-P_00_A3
S29GL-P MirrorBit
TM
Flash Family
53
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 11.7
Reset Timings
Note
CE#, OE# and WE# must be at logic high during Reset Time.
Notes
1. V
IO
< V
CC
+ 200 mV.
2. V
IO
and V
CC
ramp must be synchornized during power up.
3. If RESET# is not stable for t
VCS
or t
VIOS
:
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
4. V
CC
maximum power-up current (RST=V
IL
) is 20 mA.
Table 11.5
Power-up Sequence Timings
Parameter
Description
Speed
Unit
t
VCS
Reset Low Time from rising edge of V
CC
(or last Reset pulse) to
rising edge of RESET#
Min
35
μs
t
VIOS
Reset Low Time from rising edge of V
IO
(or last Reset pulse) to
rising edge of RESET#
Min
35
μs
t
RH
Reset High Time before Read
Max
200
ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
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