參數(shù)資料
型號(hào): S29GL128P11FFI013
廠商: SPANSION LLC
元件分類(lèi): PROM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述: 128M X 1 FLASH 3V PROM, 110 ns, PBGA64
封裝: 13 X 11 MM, 1 MM PITCH, LEAD FREE, FBGA-64
文件頁(yè)數(shù): 8/71頁(yè)
文件大?。?/td> 990K
代理商: S29GL128P11FFI013
6
S29GL-P MirrorBit
TM
Flash Family
S29GL-P_00_A3 November21,2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
2.
Input/Output Descriptions & Logic Symbol
Table 2.1
identifies the input and output package connections provided on the device.
Table 2.1
Input/Output Descriptions
Symbol
Type
Description
A25–A0
Input
Address lines for GL01GP
A24–A0 for GL512P
A23–A0 for GL256P,
A22–A0 for GL128P.
DQ14–DQ0
I/O
Data input/output.
DQ15
I/O
DQ15: Data input/output in word mode .
A-1: LSB address input in byte mode.
CE#
Input
Chip Enable.
OE#
Input
Output Enable.
WE#
Input
Write Enable.
V
CC
V
IO
V
SS
NC
Supply
Device Power Supply.
Supply
Versatile IO Input.
Supply
Ground.
No Connect
Not connected internally.
RY/BY#
Output
Ready/Busy. Indicates whether an Embedded Algorithm is in progress or complete. At
V
IL
, the device is actively erasing or programming. At High Z, the device is in ready.
Selects data bus width. At V
IL
, the device is in byte configuration and data I/O pins DQ0-
DQ7 are active. At V
IH
, the device is in word configuration and data I/O pins DQ0-DQ15
are active.
BYTE#
Input
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#/ACC
Input
Write Protect/Acceleration Input. At V
IL
, disables program and erase functions in the
outermost sectors. At V
HH
, accelerates programming; automatically places device in
unlock bypass mode. Should be at V
IH
for all other conditions.
Reserved for future use.
RFU
Reserved
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