參數(shù)資料
型號(hào)： S29GL128N11FFIV13
廠(chǎng)商： SPANSION LLC
元件分類(lèi)： DRAM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology
中文描述： 8M X 16 FLASH 3V PROM, 110 ns, PBGA64
封裝： 13 X 11 MM, LEAD FREE, FBGA-64
文件頁(yè)數(shù)： 15/100頁(yè)
文件大?。?/td> 952K
代理商： S29GL128N11FFIV13
S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit Flash Family
13
D a t a S h e e t
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are ini-
tiated through the internal command register. The command register itself does not occupy
any addressable memory location. The register is a latch used to store the commands, along
with the address and data information needed to execute the command. The contents of the
register serve as inputs to the internal state machine. The state machine outputs dictate the
function of the device.
Table 1
lists the device bus operations, the inputs and control levels
they require, and the resulting output. The following subsections describe each of these op-
erations in further detail.
Table 1. Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5 V, V
HH
= 11.5–12.5V, X = Don’t Care, SA = Sector
Address, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are AMax:A0 in word mode; A
Max
:A-1 in byte mode. Sector addresses are A
Max
:A16 in both modes.
2. If WP# = V
IL
, the first or last sector group remains protected. If WP# = V
IH
, the first or last sector is protected or
unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when
shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
3. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see
Figure 2
,
Figure 4
,
and
Figure 5
).
W ord/ Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word config-
uration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are
active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins
DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are
tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
VersatileI O
TM
( V
I O
) Control
The
VersatileI O
TM
(V
IO
) control allows the host system to set the voltage levels that the de-
vice generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted
on V
IO
. See Ordering Information for V
IO
options on this device.
For example, a V
I/O
of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and
receiving signals to and from other 1.8 or 3 V devices on the same data bus.
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read
L
L
H
H
X
A
IN
D
OUT
D
OUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
L
H
L
H
Note 2
A
IN
(Note 3)
(Note
3)
Accelerated Program
L
H
L
H
V
HH
A
IN
(Note 3)
(Note
3)
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
High-Z
High-Z
High-Z
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