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參數(shù)資料
| 型號： | S29GL128N10FAIV10 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| 中文描述： | 8M X 16 FLASH 3V PROM, 100 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 59/100頁 |
| 文件大?。?/td> | 952K |
| 代理商： | S29GL128N10FAIV10 |
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S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit Flash Family
57
D a t a S h e e t
tion. If that occurs, the chip erase command sequence should be reinitiated once the device
has returned to reading array data, to ensure data integrity.
Figure 4, on page 58
illustrates the algorithm for the erase operation.
Note that the Secured
Silicon Sector, autoselect, and CFI functions are unavailable w hen an erase opera-
tion in is progress.
Refer to the table
Erase and Program Operations on page 80
for
parameters, and
Figure 16, on page 82
section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command.
Table 12 on page 63
and
Table 14 on page 65
shows the address and data require-
ments for the sector erase command sequence.
The device does
not
require the system to preprogram prior to erase. The Embedded Erase
algorithm automatically programs and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or timings during
these operations.
After the command sequence is written, a sector erase time-out of 50 μs occurs. During the
time-out period, additional sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence, and the number of sectors may
be from one sector to all sectors. The time between these additional cycles must be less than
50 μs, otherwise erasure may begin. Any sector erase address and command following the
exceeded time-out may or may not be accepted. It is recommended that processor interrupts
be disabled during this time to ensure all commands are accepted. The interrupts can be
re-enabled after the last Sector Erase command is written.
Any command other than Sec-
tor Erase or Erase Suspend during the time-out period resets the device to the read
mode.
Note that the Secured Silicon Sector, autoselect, and CFI functions are un-
av ailable w hen an erase operation in is prog ress.
The system must rewrite the
command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See
DQ3:
Sector Erase Timer on page 72
.). The time-out begins from the rising edge of the final WE#
pulse in the command sequence.
When the Embedded Erase algorithm is complete, the device returns to reading array data
and addresses are no longer latched. The system can determine the status of the erase op-
eration by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation
Status section for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All
other commands are ignored. However, note that a
hardw are reset
immediately
terminates
the erase operation. If that occurs, the sector erase command sequence should be reinitiated
once the device has returned to reading array data, to ensure data integrity.
Figure 4, on page 58
illustrates the algorithm for the erase operation. Refer to the table
Erase
and Program Operations on page 80
for parameters, and
Figure 16, on page 82
for timing
diagrams.
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