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November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit
Flash Family
69
D a t a
S h e e t
Figure 15.7
Chip/Sector Erase Operation Timings
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see
Write Operation Status on page 55
.)
2. Illustration shows device in word mode.
Figure 15.8
Data# Polling Timings (During Embedded Algorithms)
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
t
RB
t
BUSY
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
CH
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
POLL
t
ACC
t
CE
t
OEH
t
DF
t
OH
t
RC