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參數(shù)資料
| 型號： | S29GL064M90TCIR13 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology |
| 中文描述： | 4M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | LEAD FREE, TSOP-48 |
| 文件頁數(shù)： | 25/116頁 |
| 文件大小： | 1656K |
| 代理商： | S29GL064M90TCIR13 |
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October 10, 2006 S29GL-M_00_B6
S29GL-M MirrorBit
TM
Flash Family
23
D a t a S h e e t
The internal state machine is set for reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register con-
tents are altered.
See
Reading Array Data
for more information. See
AC Characteristics
for timing specifications and
the timing diagram. See
DC Characteristics
for the active current specification on reading array
data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM
read operation. This mode provides faster read access speed for random locations within a page.
The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher
address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the
specific word within a page. This is an asynchronous operation; the microprocessor supplies the
specific word location.
The random or initial page access is equal to t
ACC
or t
CE
and subsequent page read accesses (as
long as the locations specified by the microprocessor falls within that page) is equivalent to t
PACC
.
When CE# is deasserted and reasserted for a subsequent access, the access time is t
ACC
or t
CE
.
Fast page mode accesses are obtained by keeping the “read-page addresses” constant and
changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive WE# and CE# to V
IL
, and OE# to V
IH
.
The device features an
Unlock Bypass
mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of
four.
Word Program Command Sequence
contains details on programming data to the device
using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 6
and
Table 16
indicates the address space that each sector occupies.
See
DC Characteristics
for the active current specification for the write mode.
AC Characteristics
contains timing specification tables and timing diagrams for write operations.
W rite Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard pro-
gramming algorithms. See
Write Buffer Programming
for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two
functions provided by the WP#/ACC or ACC pin, depending on model number. This function is pri-
marily intended to allow faster manufacturing throughput at the factory.
If the system asserts V
HH
on this pin, the device automatically enters the aforementioned Unlock
Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage
on the pin to reduce the time required for program operations. The system would use a two-cycle
program command sequence as required by the Unlock Bypass mode. Removing V
HH
from the
WP#/ACC or ACC pin, depending on model number, returns the device to normal operation.
Note
that the WP#/ACC or ACC pin must not be at V
HH
for operations other than accelerated program-
ming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at
V
IH
.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See
Autoselect
Mode
and
Autoselect Command Sequence
for more information.
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| S29GL064M90TCIR33 | 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology |
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| S29GL064M90TCIR42 | 256,128,64,32,Megabit 3.0 Volt-only Page Mode Flash Memory featuring 0.23 レm MirrorBit Process Technology |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL064M90TFIR20 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 90ns 56-Pin TSOP Tray |
| S29GL064M90TFIR30 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 90ns 48-Pin TSOP Tray |
| S29GL064M90TFIR4 | 制造商:Spansion 功能描述:IC,EEPROM,NOR FLASH,4MX16/8MX8,CMOS,TSSOP,48PIN,PLASTIC |
| S29GL064M90TFIR40 | 制造商:Spansion 功能描述:Flash Mem Parallel 3V/3.3V 64M-Bit 8M x 8/4M x 16 90ns 48-Pin TSOP Tray 制造商:Spansion 功能描述:IC,EEPROM,NOR FLASH,4MX16/8MX8,CMOS,TSSOP,48PIN,PLASTIC |
| S29GL064M90TFIR60 | 制造商:Spansion 功能描述:Flash Mem Parallel 3.3V 64M-Bit 4M x 16 90ns 48-Pin TSOP Tray |
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