- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄231009 > S29CL032J0RQAM013 (SPANSION LLC) 1M X 32 FLASH 3.3V PROM, 48 ns, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | S29CL032J0RQAM013 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PQFP80 |
| 封裝： | PLASTIC, MO-108CB-1, QFP-80 |
| 文件頁數(shù)： | 19/79頁 |
| 文件大?。?/td> | 2994K |
| 代理商： | S29CL032J0RQAM013 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
26
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B3 March 30, 2009
Da ta
Sh e e t
Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 4 Double Word Burst Operation
Note
Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst,
output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.
8.4.2
Initial Burst Access Delay
Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.
Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon
a rising ADV# edge, whichever comes first. The Initial Burst Access Delay is determined in the Configuration
Register (CR13-CR10). Refer to Table 8.5 for the initial access delay configurations under CR13-CR10. See
Figure 8.4 for the Initial Burst Delay Control timing diagram. Note that the Initial Access Delay for a burst
access has no effect on asynchronous read operations.
Table 8.3 Valid Configuration Register Bit Definition for IND/WAIT#
CR9
(DOC)
CR8
(WC)
CR6
(CC)
Definition
0
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
01
1
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising
CLK edge
CE#
CLK
ADV#
Addresses
OE#
Data
Address 1
Address 2
Invalid
D1
D2
D3
D0
Address 1 Latched
3 Clock Delay
IND/WAIT#
VIL
VIH
Table 8.4 Burst Initial Access Delay
CR13
CR12
CR11
CR10
Initial Burst Access (CLK cycles)
000
1
3
001
0
4
001
1
5
010
0
6
010
1
7
0
1
0
8
011
1
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S71PL032J80BAW052 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71PL032J80BAW074 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71PL032JA0BAW074 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S71PL032JA0BFW0F4 | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| S29JL032H60TAI023 | 2M X 16 FLASH 3V PROM, 60 ns, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29GL016A | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAI010 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAI012 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
| S29GL016A100BAIR10 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit, 32 Megabit, and 16 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 200 nm MirrorBit Process Technology |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。