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參數(shù)資料
| 型號： | S29CD016J1MFFI100 |
| 廠商： | Spansion Inc. |
| 英文描述： | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| 中文描述： | 32/16兆位的CMOS 2.6伏或3.3伏，只有同時讀/寫，雙啟動，突發(fā)模式閃存記憶體與VersatileI /輸出 |
| 文件頁數(shù)： | 45/76頁 |
| 文件大小： | 1245K |
| 代理商： | S29CD016J1MFFI100 |
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September27,2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
43
D a t a
S h e e t
( P r e l i m i n a r y )
If the system asserts V
IL
on the WP# pin, the device disables program and erase functions in the two
“outermost” boot sectors (8-Kbyte sectors) in the large bank. If the system asserts V
IH
on the WP# pin, the
device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector
protection or unprotection for these sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may
result.
The WP# pin must be held stable during a command sequence execution
9.6.2
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control inputs to prevent unintentional writes when V
CC
is greater than V
LKO
.
9.6.3
Write Pulse “Glitch Protection”
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
9.6.4
Power-Up Write Inhibit
If WE# = CE# = RESET# = V
IL
and OE# = V
IH
during power-up, the device does not accept commands on the
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
9.6.5
V
CC
and V
IO
Power-up And Power-down Sequencing
The device imposes no restrictions on V
CC
and V
IO
power-up or power-down sequencing. Asserting RESET#
to V
IL
is required during the entire V
CC
and V
IO
power sequence until the respective supplies reach the
operating voltages. Once, V
CC
and V
IO
attain the operating voltages, deassertion of RESET# to V
IH
is
permitted.
9.6.6
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
, or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero (V
IL
) while OE# is a logical one (V
IH
).
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| S29CD016J1MFFI102 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFI103 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFI133 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFM000 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29CD016J1MFFI102 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFI103 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFI133 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFM000 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J1MFFM002 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
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