- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365386 > S29CD016J0JQFI003 (SPANSION LLC) 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O PDF資料下載
參數(shù)資料
| 型號： | S29CD016J0JQFI003 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 54 ns, PQFP80 |
| 封裝： | LEAD FREE, PLASTIC, MO-108CB-1, QFP-80 |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 1245K |
| 代理商： | S29CD016J0JQFI003 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
20
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
D a t a
S h e e t
( P r e l i m i n a r y )
8.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from
one memory location at a time. Addresses are presented to the device in random order, and the propagation
delay through the device causes the data on its outputs to arrive asynchronously with the address on its
inputs.
The internal state machine is set for asynchronously reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs produce valid data on the device data outputs. The
device remains enabled for read access until the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the
power control and should be used for device selection (CE# must be set to V
IL
to read data). OE# is the
output control and should be used to gate data to the output pins if the device is selected (OE# must be set to
V
IL
in order to read data). WE# should remain at V
IH
(when reading data).
Address access time (t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable addresses and stable CE# to valid data at the output pins. The
output enable access time (t
OE
) is the delay from the falling edge of OE# to valid data at the output pins
(assuming the addresses have been stable for at least a period of t
ACC
-t
OE
and CE# has been asserted for at
least t
CE
-t
OE
time).
Figure 8.1
shows the timing diagram of an asynchronous read operation.
Figure 8.1
Asynchronous Read Operation
Note
Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Refer to
Section 18.2,
Asynchronous Operations
on page 52
for timing specifications and to
Figure 18.2,
Conventional Read Operations Timings
on page 52
for another timing diagram. I
CC1
in the DC
Characteristics table represents the active current specification for reading array data.
8.3
Hardware Reset (RESET#)
The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0”
on this input forces the device out of any mode that is currently executing back to the reset state. RESET#
may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential
bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data
outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset
operation is internally complete. The RY/BY# pin can be used to determine when the reset operation is
complete. Since the device offers simultaneous read/write operation, the host system may read a bank after a
period of t
READY2
, if the bank was in the read/reset mode at the time RESET# was asserted. If one of the
D0
D1
D2
D
3
D
3
CE#
CLK
ADV#
Addre
ss
e
s
D
a
t
a
OE#
WE#
IND/WAIT#
V
IH
Flo
a
t
V
OH
Addre
ss
0
Addre
ss
1
Addre
ss
2
Addre
ss
3
Flo
a
t
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S29CD016J0JQFI033 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI100 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI102 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI103 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI133 | 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29CD016J0JQFI033 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI100 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI102 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI103 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
| S29CD016J0JQFI133 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。