參數(shù)資料
      型號(hào): S29CD016J0JQAI002
      廠商: SPANSION LLC
      元件分類: DRAM
      英文描述: 32/16 Megabit CMOS 2.6 Volt or 3.3 Volt-only Simultaneous Read/Write, Dual Boot, Burst Mode Flash Memory with VersatileI/O
      中文描述: 512K X 32 FLASH 2.7V PROM, 54 ns, PQFP80
      封裝: PLASTIC, MO-108CB-1, QFP-80
      文件頁(yè)數(shù): 8/76頁(yè)
      文件大?。?/td> 1245K
      代理商: S29CD016J0JQAI002
      6
      S29CD-J & S29CL-J Flash Family
      S29CD-J_CL-J_00_B1 September27,2006
      D a t a
      S h e e t
      ( P r e l i m i n a r y )
      2.
      Input/Output Descriptions and Logic Symbols
      Table identifies the input and output package connections provided on the device.
      Symbol
      Type
      Description
      A19-A0
      Input
      Address lines for S29CD-J and S29CL-J (A18-A0 for 16Mb and A19-A0 for 32Mb).
      A9 supports 12V autoselect input.
      DQ31-DQ0
      I/O
      Data input/output
      CE#
      Input
      Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
      OE#
      Input
      Output Enable. This signal is asynchronous relative to CLK for the burst mode.
      WE#
      Input
      Write Enable
      VCC
      Supply
      Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
      VIO
      Input
      VersatileI/O
      TM
      Input.
      VSS
      I/O
      Ground
      NC
      No Connect
      Not connected internally
      RY/BY#
      Output
      Ready/Busy output and open drain which require a external pull up resistor.
      When RY/BY# = V
      OH
      , the device is ready to accept read operations and commands.
      When RY/BY# = V
      OL
      , the device is either executing an embedded algorithm or the
      device is executing a hardware reset operation.
      CLK
      Input
      Clock Input that can be tied to the system or microprocessor clock and provides the
      fundamental timing and internal operating frequency.
      AVD #
      Input
      Load Burst Address input. Indicates that the valid address is present on the address
      inputs.
      IND#
      Output
      End of burst indicator for finite bursts only. IND is low when the last word in the burst
      sequence is at the data outputs.
      WAIT#
      Output
      Provides data valid feedback only when the burst length is set to continuous.
      WP#
      Input
      Write Protect Input. At V
      IL
      , disables program and erase functions in two outermost
      sectors of the large bank.
      ACC
      Input
      Acceleration input. At V
      HH
      , accelerates erasing and programming. When not used for
      acceleration, ACC = V
      SS
      to V
      CC
      .
      Hardware Reset.
      RESET#
      Input
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