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參數(shù)資料
| 型號(hào)： | S29CD016G0MFAA112 |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| 中文描述： | 32兆位（1米× 32位），16兆位（512k × 32的位），2.5伏，只有突發(fā)模式，雙啟動(dòng)，同步讀/寫(xiě)閃存與VersatileI內(nèi)存/輸出 |
| 文件頁(yè)數(shù)： | 30/87頁(yè) |
| 文件大?。?/td> | 792K |
| 代理商： | S29CD016G0MFAA112 |
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28
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
operations provide wrap around linear burst accesses. Additional options for all burst modes in-
clude initial access delay configurations (2–16 CLKs) Device configuration for burst mode
operation is accomplished by writing the Configuration Register with the desired burst configura-
tion information. Once the Configuration Register is written to enable burst mode operation, all
subsequent reads from the array are returned using the burst mode protocols. Like the main
memory access, the Secured Silicon Sector memory is accessed with the same burst or asynchro-
nous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register and
protection bits are treated as single cycle reads, even when burst mode is enabled. Read opera-
tions to these locations results in the data remaining valid while OE# is at V
IL
, regardless of the
number of CLK cycles applied to the device.
Linear Burst Read Operations
Linear burst read mode reads either 2, 4, or 8 double words (1 double word = 32 bits). (See
Table 30
for all valid burst output sequences). The IND/WAIT# pin transitions active (V
IL
) during
the last transfer of data during a linear burst read before a wrap around, indicating that the sys-
tem should initiate another ADV# to start the next burst access. If the system continues to clock
the device, the next access wraps around to the starting address of the previous burst access.
The IND/WAIT# signal remains inactive (floating) when not active. See
Table 30
for a complete
32 data bus interface order.
CE# Control in Linear Mode
The CE# (Chip Enable) pin enables the device during read mode operations. CE# must meet the
required burst read setup times for burst cycle initiation. If CE# is taken to V
IH
at any time during
the burst linear or burst cycle, the device immediately exits the burst sequence and floats the DQ
bus signal. Restarting a burst cycle is accomplished by taking CE# and ADV# to V
IL
.
ADV # Control I n Linear Mode
The ADV# (Address Valid) pin is used to initiate a linear burst cycle at the clock edge when CE#
and ADV# are at V
IL
and the device is configured for either linear burst mode operation. A burst
access is initiated and the address is latched on the first rising CLK edge when ADV# is active or
upon a rising ADV# edge, whichever occurs first. If the ADV# signal is taken to V
IL
prior to the
end of a linear burst sequence, the previous address is discarded and subsequent burst transfers
are invalid until ADV# transitions to V
IH
before a clock edge, which initiates a new burst sequence.
Table 30. 32- Bit Linear and Burst Data Order
Data Transfer Sequence ( I ndependent of the W ORD# pin)
Output Data Sequence ( I nitial Access Address)
Two Linear Data Transfers
0-1 (A0 = 0)
1-0 (A0 = 1)
Four Linear Data Transfers
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
Eight Linear Data Transfers
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29CD016G0MFAA200 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0MFAA202 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0MFAA210 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0MFAA212 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0MFAI000 | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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