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| 型號： | S29CD016G0JFFA012 |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| 中文描述： | 32兆位（1米× 32位），16兆位（512k × 32的位），2.5伏，只有突發(fā)模式，雙啟動，同步讀/寫閃存與VersatileI內(nèi)存/輸出 |
| 文件頁數(shù)： | 56/87頁 |
| 文件大?。?/td> | 792K |
| 代理商： | S29CD016G0JFFA012 |
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54
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
P r e l i m i n a r y
Table 41. Memory Array Command Definitions
Command ( Notes)
Bus Cycles ( Notes 1–4)
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read (
5
)
1
RA
RD
Reset (
6
)
1
XXX
F0
Autoselect
(
7
)
Manufacturer ID
4
555
AA
2AA
55
555
90
BA+ X00
01
Device ID (
11
)
6
555
AA
2AA
55
555
90
BA+ X01
7E
BA+ X0E
09 for
32 Mb
36 or
08 for
16 Mb
BA+ X0F
00/01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Program/Erase Suspend (
12
)
1
BA
B0
Program/Erase Resume (
13
)
1
BA
30
CFI Query (
14
,
15
)
1
55
98
Accelerated Program (
16
)
2
XX
A0
PA
PD
Configuration Register Verify (
15
)
3
555
AA
2AA
55
BA+ 555
C6
BA+ XX
RD
Configuration Register Write (
17
)
4
555
AA
2AA
55
555
D0
XX
WD
Unlock Bypass Entry (
18
)
3
555
AA
2AA
55
555
20
Unlock Bypass Program (
18
)
2
XX
A0
PA
PD
Unlock Bypass Erase (
18
)
2
XX
80
XX
10
Unlock Bypass CFI (
14
,
18
)
1
XX
98
Unlock Bypass Reset (
18
)
2
XX
90
XX
00
Legend:
BA = Bank Address. The set of addresses that comprise a bank. The
system may write any address within a bank to identify that bank for a
command.
PA = Program Address (Amax–A0). Addresses latch on the falling
edge of the WE# or CE# pulse, whichever happens later.
PD = Program Data (DQmax–DQ0) written to location PA. Data
latches on the rising edge of WE# or CE# pulse, whichever happens
first.
Notes:
1.
See
Table 27 on page 23
for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells in table denote read cycles. All other cycles are
write operations.
4.
During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
5.
No unlock or command cycles required when bank is reading
array data.
6.
The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information).
7.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID or device ID information.
See Autoselect
Command on page 43
for more information.
8.
This command cannot be executed until The Unlock Bypass
command must be executed before writing this command
sequence. The Unlock Bypass Reset command must be executed
to return to normal operation.
9.
This command is ignored during any embedded program, erase
or suspended operation.
RA = Read Address (Amax–A0).
RD = Read Data. Data DQmax–DQ0 at address location RA.
SA = Sector Address. The set of addresses that comprise a sector. The
system may write any address within a sector to identify that sector
for a command.
WD = Write Data. See
Configuration Register on page 31
definition for
specific write data. Data latched on rising edge of WE#.
X = Don’t care
10. Valid read operations include asynchronous and burst read mode
operations.
11. The device ID must be read across the fourth, fifth, and sixth
cycles. 00h in the sixth cycle indicates ordering option 00, 01h
indicates ordering option 01.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
during a sector erase operation, and requires the bank address.
13. The Program/Erase Resume command is valid only during the
Erase Suspend mode, and requires the bank address.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
15. Asynchronous read operations.
16. ACC must be at V
ID
during the entire operation of this command.
17. Command is ignored during any Embedded Program, Embedded
Erase, or Suspend operation.
18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.
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| S29CD016G0JFFA100 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFA102 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFA110 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFA112 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
| S29CD016G0JFFA200 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit) 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/ Write Flash Memory with VersatileI/O |
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