參數(shù)資料
型號： S29AL008D70MFI013
廠商： SPANSION LLC
元件分類： PROM
英文描述： 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
中文描述： 512K X 16 FLASH 3V PROM, 70 ns, PDSO44
封裝： LEAD FREE, MO-180AAA, SOP-44
文件頁數(shù)： 6/52頁
文件大小： 2004K
代理商： S29AL008D70MFI013
14
S29AL008D
S29AL008D_00_A11 February 27, 2009
Da ta
Sh e e t
7.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 12.0 ± 0.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/
7.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
Table 7.1 S29AL008D Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
Addresses
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
L
H
AIN
DOUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write
L
H
L
H
AIN
DIN
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
Sector Protect (Note 2)
LH
L
VID
Sector Address,
A6 = L, A1 = H,
A0 = L
DIN
XX
Sector Unprotect (Note 2)
LH
L
VID
Sector Address,
A6 = H, A1 = H,
A0 = L
DIN
XX
Temporary Sector Unprotect
X
VID
AIN
DIN
High-Z
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