
20
S29AL004D
S29AL004D_00_A1  February 18, 2005
A d v a n c e  I n f o r m a t i o n
program set-up command. The program address and data are written next, which 
in turn initiate the Embedded Program algorithm. The system is 
not
 required to 
provide further controls or timings. The device automatically provides internally 
generated program pulses and verifies the programmed cell margin. 
Table  on 
page 24
 shows the address and data requirements for the byte program com-
mand sequence.
When the Embedded Program algorithm is complete, the device then returns to 
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See 
 Write Operation Status on page 26
 for information on these status bits. 
Any commands written to the device during the Embedded Program Algorithm 
are ignored. Note that a 
hardware reset
 immediately terminates the program-
ming operation. The program command sequence should be reinitiated once the 
device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. 
A bit 
cannot be programmed from a 
0
 back to a 
1
. 
Attempting to do so may halt 
the operation and set DQ5 to 
1
, or cause the Data# Polling algorithm to indicate 
the operation was successful. However, a succeeding read shows that the data is 
still 
0
. Only erase operations can convert a 
0
 to a 
1
.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the 
device faster than using the standard program command sequence. The unlock 
bypass command sequence is initiated by first writing two unlock cycles. This is 
followed by a third write cycle containing the unlock bypass command, 20h. The 
device then enters the unlock bypass mode. A two-cycle unlock bypass program 
command sequence is all that is required to program in this mode. The first cycle 
in this sequence contains the unlock bypass program command, A0h; the second 
cycle contains the program address and data. Additional data is programmed in 
the same manner. This mode dispenses with the initial two unlock cycles required 
in the standard program command sequence, resulting in faster total program-
ming time. 
Table  on page 24
 shows the requirements for the command 
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-
pass Reset commands are valid. To exit the unlock bypass mode, the system 
must issue the two-cycle unlock bypass reset command sequence. The first cycle 
must contain the data 90h; the second cycle the data 00h (F0h). Addresses are 
don’t care for both cycles. The device then returns to reading array data.
Figure 3, on page 21
 illustrates the algorithm for the program operation. See 
Table 12 on page 41
 for parameters, and 
Figure 17, on page 42
 for timing 
diagrams.