參數(shù)資料
型號(hào): S25FL008A
廠商: Spansion Inc.
英文描述: 8-Megabit CMOS 3.0 Volt Flash Memory with 50 MHz SPI (Serial Peripheral Interface) Bus
中文描述: 8兆閃存的CMOS 3.0伏,50兆赫SPI存儲(chǔ)器(串行外設(shè)接口)總線
文件頁數(shù): 18/32頁
文件大?。?/td> 719K
代理商: S25FL008A
16
S25FL008A
S25FL008A_00_B0 August31,2006
D a t a
S h e e t
Figure 9.5
Write Disable (WRDI) Command Sequence
9.6
Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits.
Table 9.2
shows
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress.
Figure 9.6
shows the RDSR command
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
Figure 9.6
Read Status Register (RDSR) Command Sequence
0
1 2
3
4 5
6 7
Comm
a
nd
C
S
#
Hi-Z
S
CK
S
I
S
O
Mode
3
Mode 0
Table 9.2
S25FL008A Status Register
Bit
Status Register Bit
Bit Function
Description
7
SRWD
Status Register Write Disable
1 = Protects when W# is low
0 = No protection, even when W# is low
6
Not used
5
Not used
4
BP2
Block Protect
000–111 = Protects upper half of address range in 5 sizes. See
Table 7.1
.
3
BP1
2
BP0
1
WEL
Write Enable Latch
1 = Device accepts Write Status Register, program, or erase
commands
0 = Ignores Write Status Register, program, or erase commands
0
WIP
Write in Progress
1 = Device Busy. A Write Status Register, program, or erase
operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
Comm
a
nd
Hi-Z
M
S
B
M
S
B
S
t
a
t
us
Regi
s
ter O
u
t
S
t
a
t
us
Regi
s
ter O
u
t
0
15
14
1
3
12
11
10
9
8
7
6
5
4
3
2
1
7 6
5
4
3
2
1 0
7
6
5 4
3
2
1
0
7
S
O
S
I
S
CK
C
S
#
Mode
3
Mode 0
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