參數(shù)資料
型號(hào)： S25FL004AOLNFI001
廠商： Spansion Inc.
英文描述： 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述： 4兆位閃存的CMOS 3.0伏，50赫茲SPI總線接口內(nèi)存
文件頁(yè)數(shù)： 10/39頁(yè)
文件大?。?/td> 945K
代理商： S25FL004AOLNFI001
8
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
Signal Description
Signal Data Output (SO):
This output signal is used to transfer data serially out
from the device. Data is shifted out on the falling edge of Serial Clock (SCK).
Serial Data Input (SI):
This input signal is used to transfer data serially into
the device. It receives instructions, addresses, and the data to be programmed.
Values are latched on the rising edge of Serial Clock (SCK).
Serial Clock (SCK):
This input signal provides the serial interface timing. In-
structions, addresses, and data present at the Serial Data input (SI) are latched
on the rising edge of Serial Clock (SCK). Data on Serial Data Output (SO) changes
after the falling edge of Serial Clock (SCK).
Chip Select (CS#):
When this input signal is High, the device is deselected and
Serial Data Output (SO) is at high impedance. Unless an internal Program, Erase
or Write Status Register cycle is in progress, the device is in Standby mode. Driv-
ing Chip Select (CS#) Low enables the device, placing it in the active power
mode.
After Power-up, a falling edge on Chip Select (CS#) is required prior to the start
of any instruction.
Hold (HOLD#):
The Hold (HOLD#) signal is used to pause any serial communi-
cations with the device without deselecting the device.
During the Hold instruction, the Serial Data Output (SO) is high impedance, and
Serial Data Input (SI) and Serial Clock (SCK) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (CS#)
driven Low.
Write Protect (W#):
The main purpose of this input signal is to freeze the area
memory size that is protected against program or erase instructions (as specified
by the values in the Status Register BP1 and BP0 bits).
SPI Modes
These devices can be driven by a microcontroller with its SPI peripheral running
in either of two modes:
CPOL = 0, CPHA = 0
CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the rising edge of Serial Clock
(SCK), and output data is available from the falling edge of Serial Clock (SCK).
The difference between the two modes, as shown in
Figure 1, on page 9
, is the
clock polarity when the bus master is in Standby and not transferring data:
SCK remains at 0 for (CPOL = 0, CPHA = 0)
SCK remains at 1 for (CPOL = 1, CPHA = 1)
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