參數(shù)資料
型號: S25FL004AOLNAI000
廠商: Spansion Inc.
英文描述: 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述: 4兆位閃存的CMOS 3.0伏,50赫茲SPI總線接口內(nèi)存
文件頁數(shù): 14/39頁
文件大小: 945K
代理商: S25FL004AOLNAI000
12
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
The Hold condition ends on the rising edge of the Hold (HOLD#) signal, provided
that this coincides with Serial Clock (SCK) being Low.
If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold
condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising
edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends
after Serial Clock (SCK) next goes Low (
Figure 3
). During the Hold condition, the
Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial
Clock (SCK) are Don’t Care.
Normally, the device remains selected, with Chip Select (CS#) driven Low, for the
entire duration of the Hold condition. This ensures that the internal logic state re-
mains unchanged from the moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has
the effect of resetting the device’s internal logic. To restart communication with
the device, it is necessary to drive Hold (HOLD#) High, and then to drive Chip
Select (CS#) Low. This prevents the device from going back to the Hold condition.
Figure 3. Hold Condition Activation
SCK
HOLD#
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
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