參數(shù)資料
型號(hào)： S25FL004AOLMFI002
廠商： Spansion Inc.
英文描述： 4-Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述： 4兆位閃存的CMOS 3.0伏，50赫茲SPI總線接口內(nèi)存
文件頁(yè)數(shù)： 12/39頁(yè)
文件大?。?/td> 945K
代理商： S25FL004AOLMFI002
10
S25FL Family (Serial Peripheral Interface) S25FL004A
S25FL004A_00_A1 March 28, 2005
A d v a n c e I n f o r m a t i o n
Operating Features
All device data into and out, is shifted in 8-bit chunks.
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN),
which is one byte, and a Page Program (PP) sequence, which consists of four
bytes plus data. This is followed by the internal Program cycle. To spread this
overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from
1
to
0
), provided that they lie in
consecutive addresses on the same page of memory.
Sector Erase, or Bulk Erase
The Page Program (PP) instruction allows bits to be programmed from 1 to 0. Be-
fore this can be applied, the memory bytes need to be first erased to all 1’s (FFh)
before any programming. This can be achieved in two ways:
A sector at a time using the Sector Erase (SE) instruction
The entire memory, using the Bulk Erase (BE) instruction
Polling During a Write, Program, or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP)
or Erase (SE or BE) can be achieved by not waiting for the worst-case delay. The
Write in Progress (WIP) bit is provided in the Status Register so that the applica-
tion program can monitor its value, polling it to establish when the previous Write
cycle, Program cycle, or Erase cycle is complete.
Active Power and Standby Power Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power
mode. When Chip Select (CS#) is High, the device is disabled, but could remain
in the Active Power mode until all internal cycles have completed (Program,
Erase, Write Status Register). The device then goes into the Standby Power
mode. The device consumption drops to I
SB
. This can be used as an extra Deep
Power Down on mechanism, when the device is not in active use, to protect the
device from inadvertent Write, Program, or Erase instructions.
Status Register
The Status Register contains a number of status and control bits, as shown in
Figure 7, on page 17
that can be read or set (as appropriate) by specific
instructions
WIP bit:
The Write In Progress (WIP) bit indicates whether the memory is
busy with a Write Status Register, Program or Erase cycle.
WEL bit:
The Write Enable Latch (WEL) bit indicates the internal Write Enable
Latch status.
BP2, BP1, BP0 bits:
The Block Protect (BP2, BP1, BP0) bits are non-volatile.
They define the area size to be software protected against Program and Erase
instructions.
SRWD bit:
The Status Register Write Disable (SRWD) bit is operated in con-
junction with the Write Protect (W#) signal. The Status Register Write Disable
(SRWD) bit and Write Protect (W#) signal allow the device to be put in the
Hardware Protected mode. In this mode, the Status Register’s non-volatile
bits (SRWD, BP2, BP1, BP0) become read-only bits.
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