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參數(shù)資料
| 型號(hào)： | S2058 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器) |
| 中文描述： | 繞道和中繼端口的光纖通道仲裁環(huán)路（用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器） |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 136K |
| 代理商： | S2058 |
3
S2058
PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP
FREQUENCY DEPENDENT JITTER
TOLERANCE
Frequency Dependent Input jitter tolerance is de-
fined as the peak to peak amplitude of sinusoidal
jitter applied on the input signal. See Figure 3.
Random Jitter Tolerance
Random Jitter Tolerance is the amount of jitter with a
gaussian distribution that the clock recovery PLL
must tolerate.
Deterministic Jitter Tolerance
Deterministic Jitter Tolerance is the amount of Deter-
ministic jitter that the clock recovery PLL must toler-
ate.
JITTER TRANSFER
Jitter transfer is defined as the ratio of jitter on the
output signal to the jitter applied on the input signal
versus frequency. Jitter transfer requirements are
shown in Figure 5. The measurement condition is
that input sinusoidal jitter up to the mask level in
Figure 4 is applied and the output jitter is measured
for compliance to the mask of Figure 5. The jitter
transfer mask includes specifications for both jitter
peaking and bandwidth.
LOCK DETECT
The S2058 lock detect circuit monitors the selected
input signal to detect the presence of the channel.
This is done by monitoring the run length, transition
density and frequency content of the incoming data.
The frequency monitor circuit checks the difference
between the divided down recovered clock and the
externally supplied reference clock (REFCLK). If the
frequency difference of the recovered clock and the
reference clock varies by more than +/- 240 ppm the
part will be declared out of lock. In the out of lock
state the PLL will lock to the local reference clock
and periodically poll the serial data input looking for
data with valid frequency content. In this state the
LOCKDET output will shift between high and low
states, mirroring the PLL as it locks to REFCLK
(LOCKDET INACTIVE) and input data (LOCKDET
ACTIVE).
Figure 3. Input Jitter Tolerance
Figure 5. Jitter Transfer Specification
Figure 4. Frequency Dependent Jitter
Tolerance Mask
FREQ DJ/ISI
RJ
10
-12
0
329
612
940
PS
BER
Jitter
Transfer
Acceptable Range
slope = -20 dB/decade
fc = 1.25 MHz
Peaking = 0.15 dB
f
/25,000
(42.5 KHz)
Cut-off Freq A
f
/1,667
(637 KHz)
Cut-off Freq B
TIME (Unit Interval - UI)
1.5
Frequency (Hz)
(KHz) = Cut-off Freq @ 1,0625 Gbps
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