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參數(shù)資料
| 型號： | S2028A |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | 32-BIT, DSP-CROSSBAR SWITCH, PQFP224 |
| 封裝： | LDCC-224 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 147K |
| 代理商： | S2028A |
3
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
Multicast Mode
In Multicast Mode, a group of 16 output channels
can be configured to connect to one input channel in
a single cycle. There are two output channel groups,
so all 32 output channels can be configured in two
cycles. Each group has its own addess range. Group
0 configures output channels 0-15 while Group 1
configures output channels 16-31. Each bit of the 16
bit data bus (CRFDATA) specifies which of the 16
output channels in the group are to be configured to
connect to the input channel.
The address bus IADDR specifies the input channel,
and the ADVERT input specifies whether to override
that input channel with the ADVERTISEP/N input.
The BANKSEL bit specifies which of the two sets of
16 output channels is being addressed. For ex-
ample, if the address bus contains “0101011001”
and the data bus contains “01000110 10101100”,
then output channels 18, 19, 21, 23, 25, 26 and 30
are configured for connection to input channel 25. If
the address bus contains “0101111001” and the data
bus is unchanged, then output channels 18, 19, 21,
23, 25, 26 and 30 are configured for connection to
the ADVERTISEP/N input.
The Multicast Address Range is from 256-511. Writ-
ing to address range 256-383 will maintain the prior
configuration for a particular channel, if that
channel’s output mask bit is set to a “0”. The ad-
dress range 384-511 activates the “break” feature of
the S2028A 33X32 Crosspoint Switch. In this mode,
for each output channel whose mask bit is set to 0, if
the prior configured input channel matches the new
requested input channel, the prior configuration is
broken and the ADVERTISE input is connected to
that output.
Unicast Mode
Writing to the Unicast Address Range (0-255) will
configure the input channel specified on the address
bus (IADDR) to connect to the output channel speci-
fied on the lower 5 bits of the data bus (OADDR).
However, if the ADVERT bit is set to a 1, IADDR is
ignored and the output channel OADDR is config-
ured to connect to the ADVERTISEP/N input.
Writing to Address Range 0-127 will maintain the
prior configuration for a particular channel, if that
channel’s output mask bit is set to a “0”. The ad-
dress range 128-255 activates the “break” feature. In
this mode, for each output channel whose mask bit
is set to 0, if the prior configured input channel
matches the new requested input channel, the prior
configuration is broken and the ADVERTISE input is
connected to that output.
Reconfiguration
When the differential switch is to be reconfigured,
the S2028A minimizes the time required through the
use of an active configuration latch. While the switch
is operational, and prior to the time at which it must
be reconfigured, a new configuration can be loaded
into the output pair configuration registers. Once the
32 output pair configuration registers contain the de-
sired connection and output pair driver control
information, the contents of the registers are trans-
ferred in parallel to the active configuration latch by
the CONFIGN strobe.This allows multiple connec-
tions to be simultaneously changed. Broadcast
mode is a single cycle operation and does not re-
quire strobing CONFIGN.
The configuration latch can be made transparent by
tying the CONFIGN input to a logic 0. When this is
done, changes strobed into the output pair configu-
ration registers by the LOADN input will be passed
immediately to the switch.
Reset Behavior
When the RESETN input is asserted, the S2028A
assumes a configuration where the ADVERTISEP/N
channel is broadcast to all of the differential output
drivers. Individual output drivers then remain in this
state after RESETN is deasserted, until they are ex-
plicitly reconfigured to a new input address.
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