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參數(shù)資料
| 型號： | S1T8527C01-Q0R0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | IC_PACKET FBGA64 10/100B-TX MINI TRANCEIVER |
| 中文描述： | 1芯片集成電路中電子系統(tǒng) |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 185K |
| 代理商： | S1T8527C01-Q0R0 |
S1T8527C
1 CHIP CLP SUBSYSTEM IC
6
33
V
CC(RX)
Supply voltage.
Supplies power to the Receiver.
34
2MO3
Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by
mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output.
35
36
2LOI
2LOI
Input terminal of second local oscillator. Generates second local oscillator frequency to
convert output from mixer 1 ( 10.7MHz ) into second intermediate frequency. It is an
oscillator with crystal of 10.24MHz and 10.245MHz.
37
2MI
Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via
10.7MHz ceramic filter. Second mixer converts frequency to second intermediate
frequency ( 455kHz: AM IF ).
38
1MO3
Output terminal of mixer 1.
The signal from mixer 1 and the frequency of the first local oscillator are mixed to
produce the first intermediate frequency, which is the output through this terminal. The
output terminal is an emitter follower with an output impedance of 330
to match the
330
input/output impedance of the 10.7MHz ceramic filter.
39
40
1LOI
1LOI
Input terminal of the first local oscillator.
The local oscillator is a voltage controlled oscillator. local oscillation frequency and
received frequency are mixed at mixer 1 and then converted to the first intermediate
frequency of 10.7MHz or 10.695MHz.
41
VCO
RX
The terminal which variable capacitor is included in the chip. Used as an input terminal
where 1st local oscillation frequency is changed by varying the capacitor connected
between 1st local oscillator terminals.The internal variable capacitor has the value of
18.73 ~ 15.86pF depending on the applied voltage. ( 1.0 ~ 2.0 V ).
42
43
1MI
1MI
Input terminal of Mixer 1. This mixer is made of double balanced multiplier.
The received signal amplified at RF AMP is input to this terminal.
44
GND
(PLL)
Ground.
Ground for analog at PLL
45
PDR
Phase detector output terminal of the receiver at PLL.
If f
RX
> f
REF
or f
RX
is Leading
→
The output is negative pulse
If f
RX
< f
REF
or f
RX
is Lagging
→
The output is positive pulse
If f
RX
= f
REF
and the same phase
→
The output is high impedance
PLL voltage reference output pin.
An internal voltage regulator provides a stable power supply voltage for the RX and TX
PLLs.
46
V
REF(PLL)
47
V
CC(PLL)
TIF
Power supply terminal of PLL.
48
Input terminal of TX channel counter.
AC coupling with TX VCO.
Minimum input level is 300mVp-p ( at 60MHz ).
PIN DESCRIPTION (Continued)
Pin No
Symbol
Description
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